Vertical Multi-Gate TFT Structure for Scaled Channel Control
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Solution Overview
Problem
Conventional thin-film transistors (TFTs) face challenges such as extrinsic resistance variation due to source and drain contact positioning errors and intrinsic resistance variation due to gate electrode dimension errors, which become more significant with scaling, limiting the commercial availability of highly-scaled TFTs.
Innovation Solution
The development of vertical thin film transistors with a gate electrode clad in a gate dielectric and a semiconductor layer, where source or drain metallization is embedded in trenches adjacent to the semiconductor layer, allowing for scalable transistor design with reduced dependence on planar dimensions, enabling more precise control over channel width and length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar TFT architecture is used, then fabrication process is simpler, but manufacturing precision deteriorates due to contact positioning errors and gate dimension variability
Solution Approach 1:
The patent transitions from a planar (2D) TFT architecture to a vertical (3D) architecture where the channel extends vertically through multiple layers. The gate electrode is positioned at the bottom, with semiconductor layers and contacts stacked above, transforming the current flow path from lateral to vertical. This dimensional change enables better control over channel dimensions and reduces sensitivity to contact positioning errors.
Solution Approach 2:
The patent inverts the conventional TFT structure by placing the gate electrode at the bottom rather than at the top or side. This inverted architecture allows the gate to control the vertical channel, with source and drain contacts positioned at the top, fundamentally reversing the traditional current flow path and control mechanism.
2Productivity
If TFT scaling is pursued to increase density, then device size is reduced, but reliability deteriorates due to increased resistance variation
Solution Approach 1:
By transitioning to vertical architecture, the patent achieves scaling in the lateral plane while maintaining controlled channel dimensions through vertical layer thickness. This allows higher device density without proportionally increasing resistance variation, as the vertical channel path can be precisely controlled through thin film deposition processes.
Solution Approach 2:
The patent utilizes changes in material parameters and layer thicknesses to control electrical characteristics. By adjusting semiconductor layer thickness, gate dielectric thickness, and contact metallization properties, the device achieves scaled dimensions with controlled resistance and leakage characteristics.
Data Source
AI summary
Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).