Vertical TFT Gate Micro-Perforations for Fast High-Current Switching
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Solution Overview
Problem
Conventional thin film transistors (TFTs) have limited transistor mobility and controllable drain current due to their planar Source-Drain structure, resulting in slow switching times and low current handling capabilities, which are not suitable for high-performance applications.
Innovation Solution
A vertical-structure TFT with a gate electrode structure, such as a comb-like or perforated structure, is employed to allow electron flow between vertically arranged source and drain electrodes, enabling high current drain and low operation voltage, with the gate electrodes being insulated by an oxide or nitride layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar Source-Drain structure with lateral active channel is used, then the device is easy to manufacture with standard thin film processes, but the transistor mobility is limited to about 10 cm2/Vs and the controllable drain current is limited to the level of mA
Solution Approach 1:
The patent transitions from a planar lateral channel structure to a vertical channel structure where the active channel extends in the vertical dimension between source and drain electrodes. This dimensional change enables much higher transistor mobility (exceeding 1000 cm2/Vs) while maintaining compatibility with standard thin film deposition and etching processes, thereby resolving the contradiction between ease of manufacture and transistor mobility.
2Ease of manufacture
If the channel length between source and drain is increased to several micrometers, then the device is easier to pattern with conventional lithography, but the switching time increases and current handling capability decreases
Solution Approach 1:
The patent employs a vertical channel structure where the channel length is extended in the vertical dimension rather than the lateral dimension. This allows the channel length to be several micrometers (easier to pattern) while the lateral footprint remains small, enabling fast switching times and high current handling capability simultaneously.
Solution Approach 2:
The patent inverts the conventional horizontal arrangement of source-channel-drain to a vertical arrangement. By stacking the source and drain electrodes vertically with the channel extending between them, the patent achieves both long channel length for easy patterning and short lateral distance for fast switching.
3Speed
If the channel layer thickness is reduced to tens of nanometers to improve switching speed, then the switching time decreases, but the controllable drain current is limited
Solution Approach 1:
The patent uses a vertical channel structure with a thin channel layer (tens of nanometers) to achieve fast switching speeds. The vertical orientation allows the thin channel to still provide sufficient cross-sectional area for high drain current by extending the channel length in the vertical dimension, thereby resolving the contradiction between switching speed and current capacity.
Solution Approach 2:
The patent changes the geometric parameters of the channel, specifically orienting it vertically and controlling its thickness at tens of nanometers. This parameter optimization enables both fast switching (due to thin channel) and high current (due to vertical extension providing sufficient conductive path area).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in high current handling capabilities and fast switching times, with drain current exceeding 0.1 A and operation voltage below 1.5V, significantly improving transistor performance compared to traditional lateral TFTs.
Implementation Method 1
The Gate electrode that controls the flow of electrons or holes between the horizontally placed Source and Drain contacts thru the semiconductor material
Data Source
AI summary
The present invention provides a vertical-type thin film transistor (TFT). The vertical TFT may comprise a source electrode and a drain electrode extending parallel to each other, with a semiconductor layer arranged in between the source electrode and the drain electrode. A single gate electrode may be embedded in the semiconductor layer, the single gate electrode comprising micro-perforations configured to control the flow of electrons therethrough in dependence on a predetermined voltage difference between the source electrode and the single gate electrode. The gate electrode masks a direct electric field between the source electrode and the drain electrode. A rate of flow of electrons through the perforations is increased with an increase in the predetermined voltage.