Vertical TFT Memory Array With Conformal Conducting Layer
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Solution Overview
Problem
As semiconductor memory devices are scaled down, they face increased variability in transistor and memory element characteristics due to process, voltage, and temperature variations, leading to design and fabrication challenges, particularly in controlling on/off currents and managing leakage currents in non-volatile memory arrays.
Innovation Solution
The implementation of a memory array with vertical bit lines connected to pairs of vertical thin-film transistors (TFTs), where the pitch is optimized by varying the separation distances between TFTs, and the use of a conformal layer of conducting material with precise etching to improve control over on/off currents and reduce fabrication costs by minimizing photolithographic steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If process geometries are shrunk to reduce cost per bit, then manufacturing cost decreases, but variability in transistor and memory element characteristics increases
Solution Approach 1:
The patent transitions from planar TFT structures to vertical TFT structures, moving the device architecture into the third dimension. This vertical configuration allows for better control of current flow paths and reduces the impact of process variability by establishing more defined electrical pathways from source to drain, thereby improving reliability while maintaining scaled geometries
Solution Approach 2:
The patent modifies key structural parameters including TFT channel length, gate width, and vertical stacking configuration. By optimizing these parameters in the vertical architecture, the design achieves improved control over transistor characteristics and memory element performance, reducing variability while maintaining cost-effective scaling
2Reliability
If vertical TFT structures are implemented with varying separation distances, then control of on/off currents is improved, but device complexity increases
Solution Approach 1:
The patent applies different separation distances (pitch) between vertical TFT structures in different regions of the memory array. By locally optimizing the pitch between adjacent vertical TFTs, the design achieves improved control over on/off current ratios in specific areas where it is most critical, while maintaining simpler configurations in other regions
Solution Approach 2:
The memory array is divided into multiple blocks or regions, each with optimized vertical TFT pitch configurations. This segmentation allows different separation distances to be applied to different functional regions, managing complexity through modular design while achieving improved current control where needed
3Reliability
If conformal layer of conducting material is deposited with precise thickness control, then leakage current is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The conformal conducting material layer is designed to automatically form isolation regions between vertical TFTs through its own deposition and subsequent anisotropic etching. The layer thickness is specifically controlled to enable self-formed spacing, where the material's own properties and the etching process work together to create proper isolation without requiring additional complex patterning steps
Solution Approach 2:
The conformal conducting material layer serves as an intermediary element that provides both electrical connection and physical isolation functions. By carefully controlling its thickness, it acts as a mediator that prevents direct contact between adjacent vertical TFT structures, reducing leakage current while the anisotropic etching process removes excess material to form proper spacing
4Ease of manufacture
If photolithographic steps are minimized, then fabrication cost is reduced, but manufacturing precision may be compromised
Solution Approach 1:
The patent extracts and eliminates certain photolithographic patterning steps from the conventional fabrication process. By using self-aligned processes and the self-formed spacing approach with conformal layers, designs that would traditionally require multiple lithography steps are achieved with fewer steps, reducing cost while maintaining precision through self-alignment
Data Source
AI summary
Systems and methods for implementing a memory array comprising vertical bit lines that are connected to different pairs of vertical thin-film transistors (TFTs) are described. A set of vertical TFTs may be formed such that a first TFT and a second TFT are spaced apart by a first separation distance and a third TFT and the second TFT are spaced apart by a second separation distance. The fabrication of the memory array includes forming a layer of conducting material with a thickness that is greater than half of the first separation distance and less than half of the second separation distance and then performing an anisotropic etch to remove portions of the conducting material such that openings in the conducting material are formed between the pairs of vertical TFTs while preventing openings from forming between the vertical TFTs of each pair of vertical TFTs.