Vertical Thin-Film Transistors for 3D Memory Bit-Line Connectors

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Solution Overview

Problem

Existing 3-D memory arrays face challenges in efficiently connecting bit lines to sense amplifiers due to the large semiconductor area required for bit-line selectors, which increases with the number of levels in the array, potentially exceeding the footprint of the memory array itself.

Innovation Solution

The implementation of vertical thin-film transistors (TFTs) above, below, or alongside the staircase structure in 3-D memory arrays, reducing the need for additional conductive layers and minimizing the footprint by allowing current flow perpendicular to the semiconductor substrate, thus reducing the required semiconductor area for bit-line selectors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If traditional horizontal thin-film transistors are used to connect bit lines to sense amplifiers, then the memory array can be formed with multiple levels, but the semiconductor area required for bit-line selectors increases with the number of levels, potentially exceeding the footprint of the memory array itself

Engineering Contradiction:

Improvenumber of memory levelsVSAvoidsemiconductor area for bit-line selectors

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent transitions from horizontal thin-film transistors to vertical thin-film transistors, changing the current flow direction from in-plane to perpendicular-to-substrate. This dimensional change allows bit-line selector transistors to be stacked vertically, reducing the semiconductor area required for bit-line selectors while supporting increased memory array levels

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If vertical thin-film transistors are implemented to reduce semiconductor area, then the footprint is minimized, but additional processing steps are required to form the vertical structure

Engineering Contradiction:

Improvesemiconductor area for bit-line selectorsVSAvoidfabrication process complexity

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent combines the formation of vertical thin-film transistors with the existing memory array fabrication process. The vertical TFT structures are integrated into the same processing sequence as the memory cells, sharing common deposition and patterning steps, which reduces overall device complexity despite the vertical architecture

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11610914B2Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays

Publication Date: 2023.03.21 SUNRISE MEMORY CORP

AI summary

A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.