Vertical Transistor Circuit Layout for 3D Memory Area Saving
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Solution Overview
Problem
Current 3D memory technologies face challenges with large chip area occupation due to the use of planar MOS select transistors, which require complex manufacturing processes and high costs, limiting the integration of peripheral circuits.
Innovation Solution
A vertical transistor circuit with perpendicular row and column lines, featuring opposite doping types in hole segments, allowing for efficient integration without active substrate area usage and enabling high driving capability with low turn-on voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If planar MOS select transistors are used for vertical bit lines, then the select transistor function is achieved, but the chip area occupied increases and peripheral circuits cannot be integrated
Solution Approach 1:
The patent transitions from planar MOS transistors to vertical transistors, changing the dimensional orientation of the select transistor from horizontal to vertical. This allows the transistor to be stacked above the memory array rather than occupying lateral space, enabling peripheral circuits to be integrated in the freed chip area.
Solution Approach 2:
The vertical transistor structure is segmented into distinct regions: the channel region formed by intersecting row and column lines, the source region, and the drain region. This segmentation allows for optimized doping profiles and selective contact formation, achieving both compact footprint and proper transistor functionality.
2Area of stationary object
If vertical MOS select transistors are disposed under the 3D memory array, then chip area is saved, but peripheral circuits are forced outside the array occupying additional area
Solution Approach 1:
Instead of placing select transistors under the memory array as conventional approaches do, the patent inverts this arrangement by positioning vertical select transistors above the memory array. This inversion allows peripheral circuits to be integrated within the chip area without being pushed to the edges.
3Adaptability or versatility
If vertical MOS select transistors are positioned on top of the substrate, then peripheral circuits can be integrated, but complex high-temperature annealing processes are required
Solution Approach 1:
The patent changes the doping parameters and material composition to achieve selective doping without requiring high-temperature annealing. By using opposite doping types in different segments and forming channels through intersecting lines, the process avoids the need for complex out-diffusion annealing while maintaining transistor functionality.
4Reliability
If MOS select transistors with dimensions limited by planar processes are used, then transistor function is achieved, but the subsequently stacked 3D memories occupy large chip area
Solution Approach 1:
The patent employs vertical transistors that extend in the vertical dimension rather than occupying lateral space. The channel is formed by the intersection of row and column lines in a vertical configuration, allowing the transistor to maintain its functional dimensions while minimizing footprint area.
Data Source
AI summary
Provided are an underlying transistor circuit of a semiconductor memory and a preparation method for the same. The circuit includes a row line layer, a column line layer positioned above the row line layer, and an insulating isolation layer between the row line layer and the column line layer, with directions of the row lines and the column lines being perpendicular to each other. Holes penetrating the column line layer and the insulating isolation layer are provided at intersections of row lines and column lines; upper and lower segments of the hole are both filled with semiconductor materials; the semiconductor material in the upper segment of the hole has a doping type the same as that of the row line, while the semiconductor material in the lower segment of the hole has a doping type opposite to that of the row line, thus, a transistor is formed in each hole.