Vertical Transistor Fabrication Preventing Channel Collapse
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Solution Overview
Problem
The challenge in fabricating vertical transistors for semiconductor devices is the collapse of cylindrical silicon patterns due to neck portions and misalignment issues during the etching process, leading to damaged gate electrodes and reduced productivity.
Innovation Solution
A method involving etching a semiconductor substrate to form pillar-type channel regions, forming buried bit lines, and creating gate electrode patterns that surround the channel regions, with additional insulating films and CMP processes to stabilize and expose surfaces, preventing pattern collapse and misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a wet etching process is performed to etch a bottom of the cylinder-type pattern to obtain a neck-shaped portion, then the channel region is formed, but the cylindrical pattern collapses due to the neck portion
Solution Approach 1:
A support layer is formed at the bottom of the cylindrical channel pattern before the wet etching process. This support layer prevents the pattern from collapsing during the formation of the neck-shaped channel region, maintaining structural integrity throughout the fabrication process.
Solution Approach 2:
The support layer acts as an intermediary element between the cylindrical channel pattern and the substrate. It provides mechanical support during the etching process and is subsequently removed after serving its protective function, allowing the channel region to maintain its desired shape without collapse.
2Manufacturing precision
If misalignment occurs during the etching process to form the gate electrode pattern, then the gate electrode is damaged, but the process control is reduced
Solution Approach 1:
A mandrel structure is formed beforehand to serve as a precise alignment reference for the gate electrode pattern. This mandrel ensures that the gate electrode is correctly positioned and prevents misalignment during the patterning process, thereby protecting the gate electrode from damage.
Solution Approach 2:
The fabrication process incorporates alignment verification steps where the position of the gate electrode pattern is checked against the mandrel structure. This feedback mechanism allows for correction of any misalignment before the gate electrode is fully formed, ensuring both precision and reliability.
3Productivity
If the area of the semiconductor device is reduced to increase integration density, then productivity is improved, but the fabrication complexity increases
Solution Approach 1:
The invention transitions from planar transistor structures to three-dimensional vertical channel structures. This dimensional change allows for higher integration density by utilizing the vertical space above the substrate, enabling more devices to be packed into the same footprint without proportionally increasing fabrication complexity.
Solution Approach 2:
The fabrication process is divided into distinct modular stages: forming the cylindrical channel pattern, adding the support layer, creating the gate electrode around the channel, and removing the mandrel. This segmentation allows each step to be optimized independently, managing overall process complexity while achieving high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the collapse of channel regions and damage to gate electrodes, enhancing process control and productivity by ensuring accurate pattern formation and increased integration density.
Implementation Method 1
etching a semiconductor substrate to form a pillar-type channel region pattern
Implementation Method 2
Impurities are ion-implanted to form an active region 140
Implementation Method 3
The exposed semiconductor substrate is oxidized to form a gate oxide film 150
Implementation Method 4
after a gate electrode 160 is deposited to surround the bottom portion 130 of the cylinder-type pattern
Implementation Method 5
after a second insulating film 190 is deposited over the damascene word line 180, a chemical mechanical polishing (CMP) process is performed to expose the top portion of the cylinder-type pattern
Data Source
AI summary
A method of fabricating a vertical transistor in a semiconductor device improves integration of the semiconductor device according to a design rule. After a semiconductor substrate is etched to form a buried bit line, a gate electrode pattern that surrounds a cylindrical channel region pattern of the vertical transistor is formed, thereby preventing damage to the gate electrode pattern due to an etching process. The gate electrode pattern surrounds the channel region pattern where a width is narrower than second source and drain regions. The second source and drain regions are then deposited over the channel region pattern and the gate electrode pattern. As a result, a neck-shaped channel region does not collapse due to the weight of the second source and drain regions.