Vertical-Transport Transistor and Fuse Integration
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Solution Overview
Problem
Current semiconductor device fabrication methods lack effective integration of vertical-transport field-effect transistors and electrical fuses into integrated circuits, which is necessary for advanced circuit designs.
Innovation Solution
A structure and method that integrate a vertical-transport field-effect transistor with a fin and a vertical electrical fuse, where the fuse link is arranged vertically between electrodes, and a gate structure is positioned between source/drain regions, using doped semiconductor layers and epitaxial growth processes to form the necessary components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional planar transistor structures are used, then fabrication processes are well-established, but integration with vertical-transport transistors and fuses is not achievable
Solution Approach 1:
The patent merges vertical-transport transistor structures with electrical fuse structures into a single integrated device. The fuse link is formed within the same semiconductor substrate as the vertical transistor channel, sharing common fabrication processes and structural elements, thereby achieving integration while managing complexity through process consolidation
Solution Approach 2:
The patent transitions from traditional planar (2D) transistor structures to vertical-transport (3D) structures where the channel extends perpendicular to the substrate surface. This dimensional change enables new integration approaches where fuses and transistors can be stacked or positioned in three-dimensional space, increasing adaptability while utilizing vertical space to manage device density
2Adaptability or versatility
If vertical-transport transistor structures are implemented, then integration with fuses becomes possible, but fabrication process complexity increases
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming the vertical transistor structure, forming the fuse link structure, and selective doping operations. Each segment uses specialized processes that can be independently optimized and controlled, making the overall complex fabrication more manageable through modular processing steps
Solution Approach 2:
The patent applies different doping conditions to different regions of the semiconductor structure. The vertical channel region receives specific doping to enable transistor operation, while the fuse link region receives different doping to enable fuse functionality. This local differentiation allows both functions to coexist in the same structure without interfering with each other's performance
3Ease of manufacture
If fuse link is placed horizontally, then fabrication is simpler, but current flow direction does not align with vertical transistor channel
Solution Approach 1:
The patent reorients the fuse link from a horizontal configuration to a vertical configuration that aligns with the vertical transistor channel. The fuse link extends in the same direction as the channel, enabling current to flow through both structures in sequence. This vertical alignment maintains fabrication simplicity by using similar vertical processing techniques while achieving proper current flow alignment
Data Source
AI summary
Structures for a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit, and methods of fabricating a vertical-transport field-effect transistor and an electrical fuse integrated into an integrated circuit. A doped semiconductor layer that includes a first region with a first electrode of the vertical electrical fuse and a second region with a first source/drain region of the vertical-transport field effect transistor. A semiconductor fin is formed on the first region of the doped semiconductor layer, and a fuse link is formed on the second region of the doped semiconductor layer. A second source/drain region is formed that is coupled with the fin. A gate structure is arranged vertically between the first source/drain region and the second source/drain region. A second electrode of the vertical fuse is formed such that the fuse link is arranged vertically between the first electrode and the second electrode.