Vertical Transistor Gate and Doped Region Configuration
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Solution Overview
Problem
The miniaturization of transistors in semiconductor devices leads to issues like short channel effects and increased leakage current, while conventional vertical transistors face challenges such as parasitic capacitance and the floating body effect, which affect device reliability and manufacturing complexity.
Innovation Solution
A transistor device design featuring shared gates and a specific doped region configuration, where the width of the gate is greater than the trench, and doped regions are strategically positioned to form vertical transistor structures, allowing for increased integration and simpler manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If physical dimensions of transistors are reduced to accelerate operating speed and miniaturize electronic devices, then operating speed and miniaturization are improved, but short channel effect and decrease in turn-on current occur
Solution Approach 1:
The patent transitions from a conventional horizontal transistor structure to a vertical transistor structure by changing the orientation of the channel from lateral to vertical. This dimensional change allows the channel to extend vertically through the substrate thickness, maintaining adequate channel length for proper current control while enabling smaller lateral footprints for higher integration density and faster operating speeds.
2Reliability
If dopant concentration in the channel region is enhanced to maintain turn-on current, then turn-on current is improved, but leakage current increases
Solution Approach 1:
The patent implements selective doping in the vertical channel structure, creating different dopant concentrations at different vertical positions and lateral regions. Specifically, the source and drain regions have higher dopant concentration to ensure adequate turn-on current, while the channel region maintains lower dopant concentration to minimize leakage current. This local quality variation allows simultaneous optimization of both turn-on current and leakage current characteristics.
3Reliability
If vertical transistor structure is adopted to avoid short channel effect, then short channel effect is avoided, but parasitic capacitance between word lines and bit lines increases
Solution Approach 1:
The patent segments the vertical channel into multiple controlled regions with different doping profiles and introduces carefully positioned doped regions that act as field plates. These segmented structures help control the electric field distribution, reducing the parasitic capacitance between adjacent word lines and bit lines while maintaining the vertical structure's advantage of avoiding short channel effects.
4Quantity of substance
If conventional method for manufacturing vertical DRAM with surround gate is used to increase memory density, then memory density is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent extracts the gate structure from the conventional surround gate configuration and replaces it with a simplified planar gate structure positioned above the vertical channel. This extraction of the complex surround gate geometry reduces the number of manufacturing steps required, simplifying the fabrication process while still achieving high memory density through the vertical channel architecture.
Data Source
AI summary
Provided is a transistor device including at least a vertical transistor structure. The vertical transistor structure includes a substrate, a dielectric layer, a gate, a first doped region, a second doped region, a third doped region, and a fourth doped region. The dielectric layer is disposed in a trench of the substrate. The gate is disposed in the dielectric layer. The gate defines, at both sides thereof, a first channel region and a second channel region in the substrate. The first doped region and the third doped region are disposed in the substrate and located below the first channel region and the second channel region, respectively. The second doped region and the fourth doped region are disposed in the substrate and located above the first channel region and the second channel region, respectively.