Vertical Channel Transistor Gate Isolation via Metal Oxide Expansion
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Solution Overview
Problem
The fabrication of vertical channel transistors in memory devices faces challenges in achieving accurate control of the control gate-to-drain overlap, which affects the threshold voltage and proper operation of the transistor, and requires sufficient isolation from the global bit line.
Innovation Solution
The process involves forming metal lines in a substrate, oxidizing regions of the metal lines to expand their height, depositing gate insulator and control gate materials, and replacing metal oxide regions with insulation to achieve consistent spacing and isolation, allowing precise control of the control gate position and overlap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal lines are oxidized to expand their height for isolation, then isolation from global bit line is improved, but manufacturing complexity increases
Solution Approach 1:
The metal lines are oxidized in advance before the control gate is formed, creating an elevated oxide structure that will later serve as the isolation layer. This preliminary oxidation action eliminates the need for separate isolation structures, reducing overall manufacturing complexity while ensuring adequate isolation.
Solution Approach 2:
The oxidized metal line serves multiple functions: it provides electrical isolation from the global bit line and simultaneously establishes the vertical spacing for the control gate. This multi-functionality reduces the number of separate process steps needed, addressing the manufacturing complexity issue.
2Manufacturing precision
If control gate position is precisely controlled for proper transistor operation, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The oxidized metal oxide layer acts as an intermediary structure that defines the vertical position of the control gate. By controlling the oxidation depth and subsequent etching, the control gate-to-drain overlap is precisely controlled without requiring complex direct positioning mechanisms.
Solution Approach 2:
The oxidation process parameters (time, temperature, atmosphere) are controlled to achieve the desired metal oxide thickness, which directly determines the control gate position. This parameter-based control simplifies the positioning process compared to mechanical or lithographic methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent transistor performance by accurately controlling the control gate position and providing adequate isolation from the global bit line, enhancing the reliability of the memory device.
Implementation Method 1
oxidizing the regions of the metal line to provide metal oxide regions
Data Source
AI summary
A fabrication process for a vertical channel transistor provides a desired control gate-to-drain overlap and sufficient isolation between the control gate and an underlying metal line. A body of the transistor is formed on a metal line, such as in a pillar shape. The metal line is oxidized to form metal oxide regions having an expanded volume. A gate insulator material and a control gate material are then deposited. The resulting structure is etched to form separate control gates for each transistor, and to expose the metal oxide. A further etch is performed to remove the metal oxide, forming voids under and around the control gates. An insulation fills the voids. An example implementation is a vertical bit line memory device in which the transistors connect a vertical bit line to a horizontal bit line.