Channel-Last Vertical Transistor Gate Length Control
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Solution Overview
Problem
The challenge in forming vertical transistors is the variability in gate length, spacer thickness, and extension doping profile due to integration challenges posed by the vertical orientation, which affects device performance, especially in scaling down to 5 nanometer devices and beyond.
Innovation Solution
A channel-last replacement metal gate all-around vertical transistor approach is adopted, where gate lengths and spacer thickness are predefined and controlled, and the source side extension is tuned by adjusting doping concentration during epitaxial growth, eliminating the reliance on etch or chemical mechanical planarization processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional vertical transistor fabrication processes are used, then device functionality is achieved, but gate length and spacer thickness exhibit high variability affecting device performance
Solution Approach 1:
The patent inverts the conventional fabrication sequence by making the channel region first through epitaxial growth, then forming the gate structure afterward. This channel-last approach reverses the traditional gate-first methodology, allowing precise control of gate length through the epitaxial growth process rather than relying on subsequent etching steps that cause variability.
Solution Approach 2:
The patent changes the fabrication parameters by using epitaxial growth conditions (temperature, pressure, gas flow, doping concentration) to precisely control channel and gate dimensions. By adjusting these growth parameters, the method achieves superior dimensional control compared to conventional lithography and etching processes.
2Ease of manufacture
If etch or chemical mechanical planarization processes are used for defining gate length, then device structure is formed, but manufacturing complexity and process variability increase
Solution Approach 1:
The patent employs self-aligned fabrication where the gate structure automatically defines the spacer positions and dimensions. The spacers are formed by depositing material on the sidewalls of the gate, eliminating the need for separate alignment and patterning steps. This self-service approach simplifies manufacturing while improving precision.
3Productivity
If scaling down to 5 nanometer devices is pursued, then technology advancement is achieved, but variability in extension doping profile increases affecting device performance
Solution Approach 1:
The patent maintains continuous epitaxial growth to form the channel and extension regions with controlled doping profiles. The doping is introduced continuously during the growth process, ensuring uniform and precise dopant distribution throughout the extended channel region, which is critical for 5nm device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures well-controlled gate lengths and spacer thickness, improving device performance by reducing variations and enhancing scalability to smaller technology nodes.
Implementation Method 1
growing an epitaxial layer within the trench to form a channel region extending from the doped source and through the sacrificial gate material; performing an epitaxial growth process to grow an epitaxial layer on a portion of the channel region to form a drain
Data Source
AI summary
A method of making a vertical transistor includes forming a doped source on a substrate; depositing a sacrificial gate material on the source; forming a trench in the sacrificial gate material to expose the doped source; growing an epitaxial layer within the trench to form a channel region extending from the doped source and through the sacrificial gate material; performing an epitaxial growth process to grow an epitaxial layer on a portion of the channel region to form a drain over the sacrificial gate material; depositing a dielectric material on the drain to form a spacer that protects the epitaxial growth; and removing the sacrificial gate material and replacing the sacrificial gate material with a gate stack that surrounds the channel region between the doped source and the drain.