Vertical Transistor Gate Routing Integration
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Solution Overview
Problem
Traditional vertical transistor architectures face processing complications due to the need for multiple routing layers and the risk of damage to the vertical channel during gate formation, which existing methodologies inadequately address, limiting scaling and integration in microchips.
Innovation Solution
A semiconductor layer is patterned into vertical semiconductor bodies, with a gate layer formed around the active channel portion, and optional electrically conductive plugs used for inter-layer routing, allowing for multi-level stacked configurations and various electrical connections, enabling the formation of advanced vertical transistor architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional vertical transistor architectures are formed with multiple routing layers, then inter-layer routing capability is improved, but processing complexity and risk of damage to vertical channel increase
Solution Approach 1:
The patent merges the gate formation process with the inter-layer routing structure by forming the gate layer to extend through the dielectric layer, creating a unified structure that serves both as a transistor gate and as an inter-layer interconnect, thereby reducing processing steps and complexity
Solution Approach 2:
The gate layer is designed to perform multiple functions: it serves as the control gate for the vertical transistor channel and simultaneously extends through the dielectric layer to function as an inter-layer interconnect for routing signals between different levels, eliminating the need for separate routing structures
2Reliability
If gate layer is formed around vertical semiconductor body, then transistor control is improved, but risk of damage to vertical channel increases
Solution Approach 1:
The patent performs preliminary actions by forming the gate layer in a controlled manner around the vertical semiconductor body using conformal deposition techniques, ensuring uniform gate thickness and proper positioning before subsequent processing steps, which prevents channel damage while achieving reliable transistor control
Solution Approach 2:
The patent introduces a dielectric layer as an intermediary between the gate layer and the vertical semiconductor channel, providing physical separation and protection during the gate formation process, thereby preventing direct contact and potential damage to the channel while still allowing electric field control
3Manufacturing precision
If vertical semiconductor bodies are patterned from semiconductor layer, then manufacturing precision is improved, but processing steps increase
Solution Approach 1:
The patent segments the processing into distinct stages: first forming the vertical semiconductor bodies through patterning, then forming the gate layer, and finally extending the gate through the dielectric layer. This segmentation allows each step to be optimized independently, achieving high vertical channel alignment precision while managing processing complexity through systematic breakdown of operations
Data Source
AI summary
Techniques are disclosed for forming vertical transistor architectures. In accordance with some embodiments, a semiconductor layer is disposed over a lower interconnect layer and patterned into a plurality of vertical semiconductor bodies (e.g., nanowires and/or other three-dimensional semiconductor structures) in a regular, semi-regular, or irregular array, as desired for a given target application or end-use. Thereafter, a gate layer surrounding the active channel portion of each (or some sub-set) of the vertical semiconductor bodies is formed, followed by an upper interconnect layer, in accordance with some embodiments. During processing, a given vertical semiconductor body optionally may be removed and, in accordance with some embodiments, either: (1) blanked to provide a dummy channel; or (2) replaced with an electrically conductive plug to provide a via or other inter-layer routing. Processing can be performed in multiple iterations, for example, to provide multi-level/stacked vertical transistor circuit architectures of any standard and/or custom configuration.