Vertical Transistor Gate Spacer Reduces Parasitic Capacitance
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Solution Overview
Problem
Vertical transistors face challenges with parasitic gate capacitance due to a large gate surface area that contacts the source layer, leading to undesirable electrostatic interactions.
Innovation Solution
A method involving the formation of a gate spacer and ultra-low-k spacer material around the gate to reduce parasitic capacitance, where a thin first gate spacer is formed on the source layer, and an additional ultra-low-k spacer is deposited to contact the sidewalls of the sacrificial gate material, replacing the sacrificial gate with a metal gate to create a recessed structure that minimizes direct contact and thus capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vertical transistor structure is used to achieve higher density scaling, then device density is improved, but parasitic gate capacitance increases due to large gate surface area contacting the source layer
Solution Approach 1:
The patent transitions from a planar gate configuration to a three-dimensional recessed gate structure. The gate is positioned in a recess formed within the gate spacer, moving the gate electrode into a lower dimension (depth) rather than expanding it horizontally. This dimensional change reduces the gate's surface area in contact with the source layer while maintaining vertical channel control, thereby reducing parasitic capacitance without sacrificing device density.
Solution Approach 2:
The patent extracts the gate electrode from direct contact with the source layer by forming a recess in the gate spacer. The gate is 'taken out' from its conventional position and placed into the recess, separating it from the source layer. This extraction eliminates the harmful parasitic capacitance interaction while preserving the gate's essential function of controlling the vertical channel.
2Object-generated harmful factors
If the gate surface area is reduced to minimize parasitic capacitance, then electrostatic control is improved, but gate contact pitch size may be compromised
Solution Approach 1:
The patent resolves this contradiction by utilizing the vertical dimension (depth) to house the gate electrode within a recess. The gate contact pitch (horizontal dimension) remains unchanged, while the gate's effective capacitance-contacting area is reduced by positioning it vertically lower in the recess. This allows the gate to maintain its electrical connection function while minimizing parasitic capacitance through vertical separation from the source layer.
Solution Approach 2:
The gate structure is segmented into distinct functional zones: the gate electrode itself (for electrical control), the gate spacer (providing structural support and defining the recess), and the recess region (providing electrical isolation). This segmentation allows the gate contact pitch to be determined by external routing requirements while the gate electrode's position in the recess independently controls parasitic capacitance.
Data Source
AI summary
A method of forming a gate spacer in a vertical transistor includes depositing a gate spacer layer on a source layer and a sacrificial gate material on the gate spacer layer; etching a trench through the sacrificial gate material and the gate spacer and forming an epitaxial channel within the trench; removing a portion of the sacrificial gate material to expose a portion of the gate spacer layer and leave the sacrificial gate material arranged on sidewalls of the channel; depositing an ultra-low-k spacer material on the gate spacer layer such that the ultra-low-k spacer material contacts a sidewall of the sacrificial gate material; and removing remaining portions of the sacrificial gate material and replacing the sacrificial gate material with a metal gate.