Vertical Transistor Electric Field Buffering for GIDL Reduction
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Solution Overview
Problem
Vertical transistors in semiconductor integrated circuit devices are prone to gate-induced drain leakage (GIDL) due to a high electric field concentration at the edge portion of the gate, which affects the channel's floated nature and increases leakage current.
Innovation Solution
A method is introduced to form an electric field-buffering region on the sidewall of the pillar in the vertical transistor, using materials with different band gaps to reduce the work function ratio between the gate and drain, thereby reducing GIDL by distributing the electric field and preventing its concentration at the gate edge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a vertical transistor with a floated channel is used to increase integration density, then more memory cells can be integrated in a small area, but gate-induced drain leakage (GIDL) increases due to high electric field concentration at the gate edge
Solution Approach 1:
An electric field buffering region is introduced as an intermediary structure between the gate and drain in the vertical transistor. This buffering region, formed with specific doping concentrations and material compositions, mediates the electric field distribution to prevent direct concentration at the gate edge, thereby reducing GIDL while preserving the vertical transistor's high integration density advantage
Solution Approach 2:
The patent applies local quality by creating regions with different doping concentrations and material properties at specific locations within the vertical transistor structure. The electric field buffering region has distinct local properties (different doping concentration, band gap) compared to the surrounding channel region, allowing targeted control of electric field distribution precisely where needed to mitigate GIDL
2Ease of operation
If voltage is applied to the gate and drain with a gate insulating layer, then the transistor can operate, but high electric field concentrates on the edge portion of the gate to generate GIDL
Solution Approach 1:
The electric field buffering region serves as a mediator between the gate and drain structures, intercepting and redistributing the electric field lines before they can concentrate at the gate edge. This intermediary structure allows normal transistor operation to proceed while preventing the harmful electric field concentration that generates GIDL
Solution Approach 2:
The patent changes physical parameters (doping concentration, material band gap) in the buffering region to alter the electric field distribution characteristics. By adjusting these parameters, the electric field is redistributed to reduce concentration at the gate edge while maintaining sufficient field strength for transistor operation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces and prevents GIDL, enhancing the reliability and performance of semiconductor integrated circuit devices by minimizing leakage current through the strategic placement and material selection of the electric field-buffering regions.
Implementation Method 1
forming an electric field-buffering region in the sidewall of the pillar... reduce the work function ratio between the gate and drain, thereby reducing GIDL by distributing the electric field and preventing its concentration at the gate edge
Data Source
AI summary
In a method of manufacturing a semiconductor integrated circuit device, a pillar may be formed on a semiconductor substrate. A hard mask pattern may be formed on a top surface and a portion of a sidewall of the pillar. An electric field-buffering region may be formed in the sidewall of the pillar. A gate insulating layer may be formed on an outer surface of the pillar. A gate may be formed on the gate insulating layer.