Vertical Transistor Top Source/Drain Junctions via Oblique Recess Etching
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Solution Overview
Problem
Vertical transistors face challenges in achieving optimal top source/drain-to-gate junction overlap, with deep fin recessing exposing and thinning the dielectric layer, leading to reliability issues and contamination, while shallow fin recessing results in underlapped junctions that degrade transistor performance.
Innovation Solution
A self-limiting fin etch is performed to form a recess with oblique sidewalls, followed by epitaxial growth of a doped top source/drain and subsequent annealing to diffuse dopants, ensuring adequate junction overlap without exposing the dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If deep fin recessing is performed to achieve adequate junction overlap, then top source/drain-to-gate junction overlap is improved, but the dielectric layer is exposed and thinned leading to reliability issues and contamination
Solution Approach 1:
The patent changes the geometric parameters of the fin structure by forming a recess with oblique sidewalls at a specific angle (e.g., 45 degrees) relative to the vertical fin sidewalls. This angular parameter change allows the recess to provide adequate junction overlap while maintaining dielectric layer coverage, resolving the contradiction between junction overlap and dielectric integrity
Solution Approach 2:
Instead of increasing recess depth in the vertical dimension (which exposes the dielectric), the patent introduces an angular dimension by forming oblique sidewalls. This dimensional change allows the recess to extend laterally to improve junction overlap while the oblique angle prevents vertical over-etching that would expose the dielectric layer
2Reliability
If shallow fin recessing is performed to protect the dielectric layer, then dielectric layer integrity is maintained, but junction overlap is insufficient degrading transistor performance
Solution Approach 1:
The patent creates an asymmetric recess structure where the sidewalls are inclined at oblique angles rather than being vertical. This asymmetry allows the recess to extend further laterally to improve junction overlap while maintaining adequate vertical depth protection for the dielectric layer, thus resolving the contradiction between dielectric integrity and junction overlap
3Ease of manufacture
If conventional vertical recessing is used, then fabrication process is simple, but junction overlap and transistor performance are insufficient
Solution Approach 1:
The patent modifies the etch process parameters to create oblique sidewalls at a controlled angle (e.g., 45 degrees). This parameter change in the etching process (such as using specific etch chemistries or angled masking) achieves improved junction overlap while maintaining a relatively straightforward fabrication workflow, balancing manufacturing simplicity with enhanced device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides improved top source/drain-to-gate junction overlap, enhancing transistor performance by preventing dielectric layer exposure and contamination, while maintaining a reliable and efficient diffusion process.
Implementation Method 1
annealing to diffuse the dopants from the top source/drain into the fin
Implementation Method 2
heating the top source/drain using a laser and then cooling to diffuse the dopant into the fin
Implementation Method 3
cooling to diffuse the dopant into the fin
Data Source
AI summary
A method of fabricating a top source/drain junction of a vertical transistor includes forming a structure including a bottom source/drain, a fin channel extending vertically from the bottom source/drain, and a gate arranged around the fin channel, the gate including a dielectric layer, a gate metal, and spacers arranged on top and bottom surfaces of the gate; etching to form a recess in a top surface of the fin, the recess having sidewalls that form oblique angles with respect to sidewalls of the fin; forming a top source/drain on the fin and within the recess; doping the top source/drain with a dopant; and annealing to diffuse the dopants from the top source/drain into the fin.