Vertical Transistor Phase Change Memory 4F2 Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices, particularly phase change memory cells, face challenges in reducing programming current and achieving efficient line and space patterning, which affects their performance and reliability.
Innovation Solution
The implementation of a 4F2 architecture with self-aligned cell contacts and a vertical strip of phase change material that is independent of lithography variations, allowing for efficient current path cross-sectional area and reduced programming current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional phase change memory cells are used with traditional lithography-based patterning, then manufacturing is straightforward, but programming current requirements are high and lithography variations affect performance
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D vertical structures. The phase change material is arranged in a vertical column between upper and lower electrodes, with the access device extending vertically. This dimensional change enables self-aligned contacts that are independent of lithography variations, reducing programming current while improving manufacturing precision.
Solution Approach 2:
The patent implements self-aligned cell contacts where the vertical structure automatically aligns the phase change material with the access device and electrodes without requiring additional lithography steps. The phase change material column is positioned to contact both the upper electrode and the access device source/drain regions automatically, eliminating alignment errors and reducing programming current.
2Manufacturing precision
If vertical transistor architecture with self-aligned contacts is implemented, then programming current is reduced and manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the vertical structure: the access device, phase change material, and electrode connections are integrated into a single vertical columnar unit. The self-aligned contact structure combines alignment and connection functions, reducing the need for separate alignment layers and reducing overall device complexity despite the vertical architecture.
Solution Approach 2:
The vertical structure serves multiple functions simultaneously: the phase change material column acts as both the memory element and the alignment reference for self-aligned contacts. The upper and lower electrodes serve both as electrical contacts and as structural elements that define the vertical geometry, reducing the need for additional alignment structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced programming current needs and improved efficiency in phase change memory cell fabrication, enhancing the performance and reliability of phase change memory devices.
Implementation Method 1
applying a programming current to a heater electrode adjacent the phase change material may heat the heater electrode, which in turn may heat the adjacent phase change material and alter the resistance state of the cell
Implementation Method 2
The phase change material may exist in an amorphous, higher resistance state, or a crystalline, lower resistance state
Data Source
AI summary
Vertical transistor phase change memory and methods of processing phase change memory are described herein. One or more methods include forming a dielectric on at least a portion of a vertical transistor, forming an electrode on the dielectric, and forming a vertical strip of phase change material on a portion of a side of the electrode and on a portion of a side of the dielectric extending along the electrode and the dielectric into contact with the vertical transistor.