Vertical Transistor Reentrant Profile Parasitic Capacitance
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in patterning vertical or inclined surfaces, leading to difficulties in controlling the thickness of deposited layers and requiring high precision alignments to reduce parasitic capacitance between electrodes in vertical transistors.
Innovation Solution
A transistor design featuring a substrate with an electrically conductive material layer stack having a reentrant profile, where a first electrically insulating material layer is positioned in contact with a portion of the conductive layer stack, and a second insulating layer is conformally coated over the first, along with a semiconductor material layer, allowing for reduced parasitic capacitance and alignment precision through a reentrant profile that shields the conductive material from directional deposition processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithographic techniques are used for vertical wall patterning, then pattern alignment can be achieved, but high precision alignment is required to reduce parasitic capacitance between electrodes
Solution Approach 1:
The gate electrode is segmented into multiple sections along the vertical wall, with insulating material layers positioned between segments. This segmentation physically separates the electrode into discrete regions, reducing parasitic capacitance between adjacent electrode portions without requiring high-precision alignment.
Solution Approach 2:
Electrically insulating material layers are introduced as intermediary elements between adjacent conductive electrode sections. These insulating layers act as mediators that electrically isolate the electrode segments from each other, reducing parasitic capacitance while simplifying the alignment requirements during fabrication.
2Quantity of substance
If deposition processes are used to coat vertical or inclined surfaces, then thin films can be deposited, but the thickness of the layer decreases as the depth of the relief increases
Solution Approach 1:
The electrode structure transitions from a planar two-dimensional configuration to a three-dimensional vertical structure with reentrant profiles. By utilizing the vertical dimension and creating overhanging sections, the design compensates for the decreasing deposition thickness at greater depths, maintaining functional electrode coverage through spatial redistribution.
Solution Approach 2:
The reentrant profile structure is formed in advance before final electrode deposition. This preliminary structural preparation creates self-shadowing effects that protect underlying regions during deposition, ensuring more uniform material distribution and consistent layer thickness throughout the vertical relief structure.
3Productivity
If vertical or inclined walls are used to create small device features, then device scaling is achieved, but parasitic capacitance increases due to electrode overlap
Solution Approach 1:
The continuous electrode structure is divided into discrete segmented sections separated by insulating material layers. This segmentation eliminates the parasitic capacitance that would exist in a continuous overlapping electrode configuration, while maintaining the scaled-down vertical device dimensions.
Solution Approach 2:
The harmful parasitic capacitance effect is extracted and eliminated by removing the continuous conductive path between electrode sections. Insulating material layers are strategically positioned to extract and isolate the capacitive coupling between adjacent vertical electrode portions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces parasitic capacitance and eliminates the need for high-resolution alignments, simplifying the manufacturing process by using a reentrant profile to separate electrodes and maintain consistent layer thickness, thereby enhancing the performance and efficiency of vertical transistors.
Implementation Method 1
using a reentrant profile to separate electrodes and maintain consistent layer thickness
Implementation Method 2
a second insulating layer is conformally coated over the first
Data Source
AI summary
A transistor includes a substrate and an electrically conductive material layer stack positioned on the substrate. The electrically conductive material layer stack includes a reentrant profile. A first electrically insulating material layer positioned is in contact with a first portion of the electrically conductive material layer stack. A second electrically insulating material layer is conformally positioned in contact with the first electrically insulating layer, and conformally positioned in contact with a second portion of the electrically conductive material layer stack, and conformally positioned in contact with at least a portion of the substrate.