Vertical Transistor Resistive Memory with Isolation Layers
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Solution Overview
Problem
Current resistive memory devices face challenges in reducing power consumption and preventing interference between memory cells, particularly in non-volatile memory devices that require efficient resistance change characteristics and effective isolation layers.
Innovation Solution
The development of a resistive memory device incorporating a vertical transistor with a single crystalline silicon layer and a variable resistance layer, where the variable resistance layer is electrically insulated from the gate electrode and isolated by a device isolation layer, allowing for efficient programming and erasing of memory cells with reduced leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional resistive memory device structure is used, then the device can store data, but power consumption is high and interference between memory cells occurs
Solution Approach 1:
The memory device is segmented into isolated memory cells using device isolation layers. Each memory cell is physically separated from adjacent cells by these isolation layers, preventing electrical interference and leakage current between cells while maintaining individual functionality.
Solution Approach 2:
Device isolation layers are introduced as intermediary structures between the variable resistance layer and the substrate, and between adjacent memory cells. These isolation layers act as mediators that block electrical interference and leakage current paths, thereby reducing power consumption and preventing cell-to-cell interference.
2Ease of operation
If the variable resistance layer is directly connected to the gate electrode, then programming is simplified, but leakage current increases and interference occurs
Solution Approach 1:
A device isolation layer is introduced as an intermediary between the variable resistance layer and the gate electrode. This isolation layer maintains electrical insulation while allowing the gate electrode to control the channel region, thereby preventing direct leakage paths while preserving programming functionality.
Solution Approach 2:
The device isolation layer is strategically positioned only where needed - between the variable resistance layer and the gate electrode, and between adjacent memory cells - rather than uniformly across the entire device. This localized approach maintains programming simplicity in functional areas while blocking leakage current in isolation areas.
3Reliability
If isolation layers are added to prevent interference, then reliability improves, but device complexity increases
Solution Approach 1:
The device isolation layer serves multiple functions simultaneously: it isolates adjacent memory cells from electrical interference, prevents leakage current between the variable resistance layer and gate electrode, and provides mechanical support. By combining these functions into a single structure, the patent achieves improved reliability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient resistance switching with reduced power consumption and minimized interference between memory cells, enhancing the performance and reliability of resistive memory devices.
Implementation Method 1
a single crystalline silicon layer on the surface of the substrate adjacent to the gate insulation layer. At least a portion of the single crystalline silicon layer defines a channel region that extends in a direction substantially perpendicular to the surface of the substrate
Implementation Method 2
resistive memory devices, such as resistive random access memory (RRAM), may offer relatively high speed, high capacity, and low power consumption characteristics
Implementation Method 3
a gate insulation layer extending along a sidewall of the gate electrode
Implementation Method 4
The device isolation layer may electrically insulate the gate electrode from the bit line
Data Source
AI summary
A resistive memory device includes a vertical transistor and a variable resistance layer. The vertical transistor includes a gate electrode on a surface of a substrate, a gate insulation layer extending along a sidewall of the gate electrode, and a single crystalline silicon layer on the surface of the substrate adjacent to the gate insulation layer. At least a portion of the single crystalline silicon layer defines a channel region that extends in a direction substantially perpendicular to the surface of the substrate. The variable resistance layer is provided on the single crystalline silicon layer. The variable resistance layer is electrically insulated from the gate electrode. Related devices and fabrication methods are also discussed.