Vertical Transistor Self-Aligned Contacts Planar Surface
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Solution Overview
Problem
Existing memory devices face challenges in integrating vertical field-effect transistors with self-aligned contacts, resulting in a non-planar surface between the memory array and peripheral circuitry, which complicates the production process and requires methods to achieve a planar or nearly planar surface for efficient memory cell formation.
Innovation Solution
The method involves forming vertical field-effect transistors with self-aligned contacts by depositing pad oxide and nitride on a substrate, creating trenches for shallow trench isolation, growing epitaxial silicon pillars, and forming gate oxides and TiN gates, allowing for the formation of self-aligned contacts that align the array and peripheral circuitry surfaces, ensuring they are nearly planar.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical field-effect transistors with self-aligned contacts are integrated into memory devices, then device performance and integration density are improved, but the surface becomes non-planar between memory array and peripheral circuitry, complicating the production process
Solution Approach 1:
The patent transitions from planar transistor architecture to vertical transistor architecture, moving the active device structure into the third dimension. This vertical configuration increases integration density by utilizing vertical space rather than horizontal space, allowing higher device packing density while maintaining self-aligned contact formation through the vertical sidewalls of the transistor structure.
Solution Approach 2:
The patent implements preliminary planarization actions by forming an intermediate structure with a planar top surface before completing the memory array formation. This intermediate structure serves as a planar platform that simplifies subsequent processing steps, allowing the memory array to be formed on a flat surface while the vertical transistors extend downward to their active regions, thus resolving the non-planar surface issue.
2Area of stationary object
If vertical transistors are used to reduce footprint, then area is saved, but achieving planar surface alignment between array and periphery requires additional process steps
Solution Approach 1:
The patent segments the device structure into distinct functional regions: vertical field-effect transistors with self-aligned contacts form the access devices, while an intermediate structure provides a planar platform for the memory array. This segmentation allows each region to be optimized independently - the vertical transistors minimize footprint while the intermediate structure provides the necessary planar surface, reducing the need for additional planarization process steps.
Solution Approach 2:
The patent introduces an intermediate structure as a mediator between the vertical transistor region and the memory array region. This intermediate structure has a planar top surface that aligns with the memory array, serving as a transition zone that facilitates planar surface alignment without requiring complex additional process steps. The intermediate structure acts as a buffer that reconciles the vertical geometry of the transistors with the planar requirements of the array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the production process by maintaining a planar surface between the array and peripheral circuitry, enabling efficient integration of vertical transistors and facilitating subsequent back-end-of-line processes without step-change issues, thereby improving manufacturing efficiency and device performance.
Implementation Method 1
depositing pad oxide and nitride on a substrate
Implementation Method 2
growing epitaxial silicon pillars
Implementation Method 3
forming gate oxides
Data Source
AI summary
Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.