Vertical Transistor SRAM Bottom Electrode Interconnection
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving area-efficient interconnections between transistors in static random access memory (SRAM) bit cells, particularly due to the need for vertical metal contacts that reduce overall area efficiency.
Innovation Solution
A semiconductor device with a bottom electrode region comprising doped regions that form p-n junctions, allowing for direct electrical interconnection of transistors without dedicated metal contacts, and a conductive pattern that provides both gate functionality and routing for the transistors, enabling compact and efficient connections between gate and bottom electrode regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical metal contacts are used to interconnect bottom source/drain regions, then electrical connection between transistors is achieved, but area efficiency of the bit cell is reduced
Solution Approach 1:
The patent merges the interconnection function with the bottom source/drain regions themselves by creating a shared connection region that directly electrically connects the bottom source/drain regions of multiple transistors. This eliminates the need for separate vertical metal contacts, thereby achieving electrical interconnection while preserving bit cell area efficiency.
Solution Approach 2:
The bottom source/drain regions are designed to serve dual functions: as the source/drain contacts for individual transistors and as the interconnection medium for electrically connecting multiple transistors together. This multi-functionality eliminates the need for dedicated interconnection structures, improving area efficiency.
2Reliability
If individual vertical metal contacts are created for each bottom source/drain, then transistor interconnection is enabled, but device integration density is reduced
Solution Approach 1:
Multiple bottom source/drain regions are merged into a shared connection region that provides common electrical access to multiple transistors. This consolidation reduces the number of separate interconnection structures needed, thereby increasing device integration density while maintaining reliable transistor interconnection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances area efficiency in SRAM circuits by eliminating the need for vertical metal contacts and reducing resistance between transistors, thereby improving scalability and thermal budget during fabrication.
Implementation Method 1
the first, the second and the third regions are doped such that a first p-n junction is formed between the first and the second region and a second p-n junction is formed between the second and third region
Data Source
AI summary
The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions. A connection region is formed in the bottom electrode region underneath the first, second and third regions, wherein the connection region and the first and third regions are doped with a dopant of a same type. A resistance of a path extending between the first and the third regions through the connection region is lower than a resistance of a path extending between the first and the third regions through the second region. A second aspect is a method of forming the semiconductor device of the first aspect.