Self-Aligned Top Contact for Vertical Transistor Resistance
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Solution Overview
Problem
Vertical transistors face performance limitations due to high resistance at the top source drain region caused by a limited contact area between the top source drain epi and the metal top contact, which is exacerbated by the constraints of current lithographic patterning in tight pitch designs, leading to potential electrical shorts between neighboring nFET and pFET devices.
Innovation Solution
A self-aligned wrap-around-contact architecture is introduced, which increases the contact area between the top source drain region and the metal top contact, allowing for full utilization of the fin length while preventing electrical shorts by aligning the top source drain region and embedding the top contact partially into it, thereby reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional top contact structure is used, then lithographic patterning is simpler, but contact area is limited and resistance is high
Solution Approach 1:
The top contact structure transitions from a planar two-dimensional contact to a three-dimensional wrap-around configuration that extends vertically along the fin sidewalls and wraps around to the top surface. This dimensional change increases the contact area by 1.5-2 times compared to conventional planar contacts, thereby reducing contact resistance and improving device performance without requiring higher lithographic precision
Solution Approach 2:
The top contact is designed to wrap around the fin structure, with portions embedded in the top source drain region and extending along the sidewalls. This nested configuration allows the contact to penetrate and surround the active region, maximizing the electrical interface area between the contact and the underlying semiconductor structure
2Reliability
If contact area is increased to reduce resistance, then device performance improves, but risk of electrical shorts between neighboring devices increases
Solution Approach 1:
The top contact structure exhibits spatially varying properties: it is embedded in the top source drain region where high electrical contact is needed, extends along the sidewalls to maximize contact area, and is positioned to avoid overlapping with adjacent device structures. This localized differentiation of contact presence and configuration allows resistance reduction without creating short circuits between neighboring nFET and pFET devices
Solution Approach 2:
By extending the contact vertically along the fin sidewalls and wrapping around to the top surface, the design utilizes the third dimension to increase contact area. This vertical extension provides additional contact pathways without requiring lateral expansion that would encroach on adjacent device pitch, thereby preventing electrical shorts while reducing resistance
Data Source
AI summary
A semiconductor structure including a bottom source drain region arranged on a substrate; a semiconductor channel region extending vertically upwards from a top surface of the bottom source drain region; a metal gate disposed around the semiconductor channel region; a top source drain region above the semiconductor channel region; and a top contact partially embedded into the top source drain region.