Vertical Transport Logic Cell Shared Pitch Area Reduction
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Solution Overview
Problem
Standard logic cells in integrated circuits require significant area, limiting the density of logic circuits and the amount of memory or computing resources that can be packed on a chip, as they are determined by minimum metal pitch and contacted polysilicon pitch, which are not efficiently optimized.
Innovation Solution
The implementation of vertical transport logic circuit cells with shared pitch areas between logic gates, allowing for reduced area usage by overlapping input and output terminals, thereby reducing the number of contacted polysilicon pitches required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If standard logic cells are used with conventional layouts, then the circuit functionality is achieved, but the area consumption is high and density is limited
Solution Approach 1:
The patent merges the pitch requirements of multiple logic gates by sharing common pitch segments. Specifically, adjacent logic gates are arranged to share contacted polysilicon pitches and metal routing pitches, combining what would traditionally be separate pitch allocations into overlapping shared resources, thereby reducing the total area required for the logic cell.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar layouts to a three-dimensional vertical transport architecture. By stacking transistor layers vertically and utilizing vertical interconnects, the design achieves higher density without increasing the planar footprint, effectively using the vertical dimension to pack more functionality into the same area.
2Area of stationary object
If the number of contacted polysilicon pitches is reduced through sharing, then area savings are achieved, but the layout complexity increases
Solution Approach 1:
The patent segments the logic cell into modular units with standardized pitch interfaces. By dividing the cell into repeating patterns of shared and dedicated pitch segments, the design achieves area efficiency while maintaining manageable complexity through modularity and regularity in the layout structure.
Solution Approach 2:
The shared pitch structures serve multiple functions simultaneously: they act as both interconnects for adjacent logic gates and as structural elements for vertical transport. This multi-functionality reduces the total number of separate components needed, thereby reducing overall layout complexity despite the innovative sharing approach.
Data Source
AI summary
A semiconductor structure includes a vertical transport logic circuit cell. The vertical transport logic cell includes a first logic gate and at least a second logic gate. The first logic gate includes at least one input terminal and at least one output terminal. The second logic gate includes at least one input terminal and at least one output terminal. One of the input terminal and the output terminal of the first logic gate shares a pitch of the vertical transport logic circuit cell with one of the input terminal and the output terminal of the second logic gate. The first and second logic gates can include the same type or different types of logic functions.