Vertical Trench Memory Cell Insulating Ring for BSOD Isolation

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Solution Overview

Problem

As semiconductor devices scale down, vertical trench memory cells face issues with buried strap outdiffusion (BSOD) merging due to reduced space between neighboring cells, leading to electrical shorts and increased susceptibility to noise and errors.

Innovation Solution

A method of forming a vertical transistor trench memory cell with an insulating ring, where the ring is formed by epitaxial growth of silicon and surrounds the trench memory cells, preventing the merging of outdiffusion regions and isolating each cell from its neighbors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If cell size is reduced by shrinking feature sizes, then chip density increases, but storage capacitance decreases and cells become more susceptible to noise and errors

Engineering Contradiction:
Improvechip densityVSAvoidstorage capacitance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from planar capacitor structures to vertical trench capacitor structures, utilizing the third dimension (depth) to maintain capacitance while reducing the planar footprint. The trench capacitor extends vertically into the substrate, increasing the effective plate area without increasing the cell's planar dimensions, thus maintaining storage capacitance while improving chip density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds the trench capacitor vertically within the substrate, nesting the storage structure within the available three-dimensional space of the memory cell. The trench capacitor is positioned beneath the transistor structure, effectively utilizing the vertical space to maintain capacitance while minimizing the planar cell area.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If space between neighboring trenches is reduced to scale devices, then device density increases, but buried strap outdiffusion regions merge causing electrical shorts

Engineering Contradiction:
Improvedevice densityVSAvoidelectrical isolation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an insulating ring structure as an intermediary element positioned between adjacent trench memory cells. This insulating ring acts as a barrier that prevents the merging of buried strap outdiffusion regions from neighboring cells, maintaining electrical isolation even when the spacing between trenches is reduced for higher device density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulating ring is formed during the fabrication process before the final device operation, preemptively creating a barrier against outdiffusion merging. By establishing this isolation structure in advance, the patent prevents the harmful effect of outdiffusion merging before it can occur during device operation or thermal processing.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively suppresses BSOD merging, allowing for the scaling of vertical transistors without the need for deep isolation, thereby maintaining storage capacitance and reducing noise susceptibility while maintaining chip density and cost efficiency.

Implementation Method 1

the ring is formed by epitaxial growth of silicon

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Implementation Method 2

at least a portion of the vertical transistor is isolated by the insulating ring

Methodology Applied
Scientific EffectElectrical insulation: Electrical Resistance

Data Source

PatentUS7528035B2Vertical trench memory cell with insulating ring
Publication Date: 2009.05.05 GLOBALFOUNDRIES US INC
  • US7528035B2 patent drawing
  • US7528035B2 patent drawing
  • US7528035B2 patent drawing

AI summary

A method of forming a vertical transistor trench memory cell having an insulating ring is provided. The method includes forming a semiconductor material region in an etched portion of a semiconductor substrate; partially etching the semiconductor material region to form a deep trench, where the deep trench extends beyond the semiconductor material region, and where the remaining of the partially etched semiconductor material region defines an insulating ring. A vertical transistor is then formed in the deep trench, such that the vertical transistor is isolated by the insulating ring. A semiconductor structure is also provided. The semiconductor structure includes a first and a second trench memory cells formed on a semiconductor substrate; and an insulating ring surrounding each of the first and second trench memory cells. The insulating ring is configured for significantly enclosing out diffusions from the trench memory cells.