Vertical Wire Semiconductor Package for Dense Chip Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packages face challenges in increasing integration density, mechanical reliability, and electrical performance, particularly when stacking multiple chips, leading to increased system board size and reduced battery capacity.
Innovation Solution
A semiconductor package design featuring a lower package with a first semiconductor chip and a second semiconductor chip spaced apart vertically, connected by a vertical wire, and an upper package with an interposer substrate, allowing for reduced mounting area and improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple semiconductor chips are stacked vertically to increase integration density, then the mounting area on the system board is reduced, but the mechanical reliability and electrical performance deteriorate due to warpage and signal transmission issues
Solution Approach 1:
The patent transitions from horizontal chip arrangement to vertical stacking configuration, moving components into the third dimension (height direction). Multiple semiconductor chips are arranged vertically along the height direction of the package body, enabling space utilization in the vertical dimension while reducing the footprint area on the system board.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor chips are stacked within a single package body. The chips are arranged in a vertical column, with each chip nested above the previous one, similar to nested dolls. This allows multiple functional units to be contained within a compact vertical space, improving integration density while maintaining a small overall package footprint.
2Area of moving object
If multiple semiconductor chips are stacked vertically to increase integration density, then the mounting area on the system board is reduced, but the electrical performance deteriorates due to increased signal transmission distance
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between the stacked semiconductor chips. The interposer substrate provides a platform with redistribution layers that facilitate short-distance electrical connections between chips. This mediator enables efficient signal transmission between vertically stacked chips while maintaining compact dimensions, thus improving electrical performance despite the vertical arrangement.
Solution Approach 2:
The patent utilizes the vertical dimension for chip stacking while employing horizontal redistribution layers on the interposer substrate for signal routing. This dimensional separation allows signals to travel short horizontal distances on each layer rather than long vertical paths, improving electrical performance by minimizing transmission distance despite the vertical chip arrangement.
3Quantity of substance
If conventional chip stacking methods are used, then integration density is improved, but manufacturing complexity and costs increase
Solution Approach 1:
The patent performs preliminary arrangement and connection of semiconductor chips and the interposer substrate before final encapsulation. The chips are pre-positioned and electrically connected in the desired vertical configuration, with wiring patterns established in advance. This preliminary organization simplifies the subsequent manufacturing steps and reduces overall manufacturing complexity while achieving high integration density.
Solution Approach 2:
The patent combines multiple manufacturing operations into an integrated process flow. The semiconductor chips are stacked, connected to the interposer substrate, and then all components are simultaneously encapsulated in a single molding operation. This merging of steps reduces the number of separate manufacturing processes required, simplifying production while maintaining high integration density.
Data Source
AI summary
A semiconductor package includes a lower package, and a substrate on the lower package, wherein the lower package comprises a lower package substrate, a first semiconductor chip on the lower package substrate such that a front side of the first semiconductor chip on which a first chip pad is formed faces the lower package substrate, a second semiconductor chip on a lower surface of the substrate and spaced apart from the first semiconductor chip in a first direction perpendicular to an upper surface of the lower package substrate, and a vertical wire connecting the lower package substrate and the second semiconductor chip in the first direction.