Vertically Offset Conductive Pillars for High-Density Interconnects
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving high routing density without electrical shorts between adjacent bumps during the bump reflow process, which can lead to bridging issues.
Innovation Solution
The implementation of vertically offset conductive pillars and interconnect structures over a substrate, where adjacent bumps are separate and overlapping, allowing for a fine pitch interconnect while maintaining physical separation to prevent electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine interconnect pitch is used to increase routing density, then interconnect capability is improved, but electrical shorts or bridging between adjacent bumps occurs during bump reflow process
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of conductive pillars to a three-dimensional vertically offset configuration. Conductive pillars are arranged in multiple vertical layers at different heights, allowing interconnects to stack above one another. This vertical dimension enables higher routing density without increasing lateral bump pitch, thereby preventing electrical shorts while maintaining fine interconnect spacing.
Solution Approach 2:
The patent segments the conductive interconnect structure into multiple discrete vertical layers or levels. Each layer contains conductive pillars at specific heights, separated by dielectric materials. This segmentation allows independent routing paths at different vertical levels, increasing overall routing capacity without requiring smaller lateral pitch that would cause bridging.
2Quantity of substance
If adjacent bumps are placed closer together to increase interconnect density, then interconnect capability is improved, but physical separation is reduced leading to electrical shorts
Solution Approach 1:
The patent utilizes the vertical dimension to increase interconnect density without reducing lateral bump pitch. By stacking conductive pillars at different vertical heights and connecting them through vertical vias, the design achieves higher interconnect capacity while maintaining adequate horizontal spacing between adjacent bumps to prevent electrical shorts.
Solution Approach 2:
The patent implements a nested structure where conductive pillars and interconnects at different vertical levels are positioned within the same lateral footprint. Lower-level conductive structures are surrounded by upper-level structures, creating a nested arrangement that maximizes interconnect density within the available area while maintaining physical separation through vertical layering.
Data Source
AI summary
A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.