High Aspect Ratio Via Barrier Layer Step Coverage
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Solution Overview
Problem
The increasing aspect ratio of vias in semiconductor devices poses challenges in achieving good step coverage of barrier layers, leading to defects such as voids and open circuit issues due to native oxide formation on sidewalls, which blocks electrical signals and degrades device reliability.
Innovation Solution
A method involving pre-treatment processes like Ar sputtering or wet clean to remove native oxide, followed by oxide etching to form a spacer around the via top corner, and subsequent deposition of barrier layers and conductive materials like tungsten using CVD, with a chemical-mechanical polishing process to ensure a clear surface for improved electrical conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the via aspect ratio is increased to achieve higher functional density, then the via depth increases, but the barrier layer step coverage deteriorates and native oxide formation blocks electrical signals
Solution Approach 1:
A preliminary oxide removal step is performed before barrier layer deposition to eliminate native oxide that would otherwise block electrical signals. This preliminary action ensures that the subsequent barrier layer can be properly deposited without interference from oxide contaminants on the via sidewalls.
Solution Approach 2:
The patent replaces conventional physical vapor deposition (PVD) with chemical vapor deposition (CVD) for barrier layer deposition. This substitution enables better step coverage in high aspect ratio vias by allowing the reactive gas to chemically react and deposit material conformally on all surfaces, including vertical sidewalls.
2Manufacturing precision
If the barrier layer film thickness is increased to improve step coverage, then coverage improves, but reactant gas attacks via sidewall silicon creating voids and open circuit issues
Solution Approach 1:
A dedicated oxide removal layer or treatment is introduced as an intermediary step between via formation and barrier layer deposition. This intermediary layer or treatment protects the via sidewall silicon from reactant gas attack while still allowing the barrier layer to deposit properly, preventing void formation and maintaining via integrity.
Solution Approach 2:
The patent modifies the deposition parameters and chemistry of the CVD process to reduce the aggressiveness of the reactant gas toward silicon sidewalls. By adjusting temperature, pressure, gas composition, or flow rates, the deposition process achieves adequate barrier layer coverage without causing excessive silicon etching that leads to voids.
3Ease of manufacture
If conventional PVD is used for barrier layer deposition, then the process is simple, but step coverage in high aspect ratio vias is insufficient
Solution Approach 1:
The patent replaces physical vapor deposition (PVD) with chemical vapor deposition (CVD) for barrier layer deposition. This substitution enables better step coverage in high aspect ratio vias by allowing the reactive gas to chemically react and deposit material conformally on all surfaces, including vertical sidewalls, overcoming the line-of-sight limitation of PVD.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the protection of sidewall silicon from attack during tungsten deposition, provides a substantially oxide-free interface for barrier layer deposition, and ensures reliable electrical connectivity by forming a flat surface for subsequent processes.
Implementation Method 1
pre treatment processes like Ar sputtering or wet clean to remove native oxide
Implementation Method 2
subsequent deposition of barrier layers and conductive materials like tungsten using CVD
Data Source
AI summary
The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.