Interconnect Via Etching with Capping Layer for Vertical Profiles
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving vertical etch profiles for vias in interconnect structures, leading to potential leakage and contact between vias and metal lines, which affects the performance of integrated circuits.
Innovation Solution
The method involves forming a metal oxide layer and an interlayer dielectric layer over an etch stop layer, followed by the deposition of a capping layer and specific etching processes to create substantially vertical via profiles, preventing over-etching and ensuring precise dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for via formation, then the manufacturing process is simple, but the etch profile is not vertical leading to leakage and contact between vias and metal lines
Solution Approach 1:
The etching process is divided into multiple sequential steps with different etch selectivities. First, a mandrel layer is formed and patterned, then a spacer layer is deposited and patterned to define via openings. The etching is performed in stages: first through the spacer layer to form via openings, then the mandrel layer is removed, and finally the via openings are etched through the interlayer dielectric to the substrate. This segmentation allows precise control of the etch profile at each stage.
Solution Approach 2:
The mandrel layer and spacer layer are formed in advance before the actual via etching. The mandrel layer is deposited and patterned first, then the spacer layer is deposited over it and patterned to define the via opening locations. These preliminary structures serve as etch masks and guides, ensuring that the subsequent etching process creates vertical via profiles with precise dimensions and correct positioning.
2Quantity of substance
If via dimensions are reduced for higher storage capacity, then storage capacity increases, but etch profile control becomes more difficult
Solution Approach 1:
Different materials with different etch selectivities are used at different locations and stages. The spacer layer material is selected to have a specific etch selectivity relative to the mandrel layer and interlayer dielectric. This allows the etching process to selectively remove materials in a controlled manner, maintaining vertical profiles even as via dimensions are reduced for higher storage capacity.
3Speed
If faster processing systems are implemented, then processing speed increases, but etch profile control deteriorates
Solution Approach 1:
The etching process parameters are optimized for each stage. Different etch chemistries, temperatures, and pressure conditions are used for etching through the spacer layer versus etching through the interlayer dielectric. By changing parameters between stages rather than using a single fast etch process, vertical profiles are maintained while achieving high processing speeds suitable for modern semiconductor manufacturing.
Data Source
AI summary
A method of forming a semiconductor structure includes forming an etch stop layer on a substrate, forming a metal oxide layer over the etch stop layer, and forming an interlayer dielectric (ILD) layer on the metal oxide layer. The method further includes forming a trench etch opening over the ILD layer, forming a capping layer over the trench etch opening, and forming a via etch opening over the capping layer.