Via Creation Method for Integrated Circuit Electrical Connectivity
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Solution Overview
Problem
The existing methods for creating vias in integrated circuit chips often result in incomplete electrical connections between metal layers due to particle contamination or poor conductive layer formation, leading to signal transmission failures.
Innovation Solution
A method is introduced where new vias are automatically created around existing ones in the circuit layout data to ensure electrical connectivity, with a computer system determining which new vias maintain or disrupt the original circuit connection, allowing only non-disruptive vias to remain, thereby enhancing the probability of successful electrical connections between metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If new vias are created around existing vias to increase connection reliability, then the probability of electrical connection is improved, but the circuit layout complexity increases
Solution Approach 1:
The patent applies preliminary action by automatically creating backup vias in advance during the design phase, before manufacturing. The system identifies existing vias and generates additional via candidates around them, then evaluates and keeps only those that don't disrupt original connections. This pre-planning ensures connection reliability without requiring manual intervention during manufacturing.
Solution Approach 2:
The patent implements self-service through an automated computer-based system that performs the entire via creation and evaluation process without human intervention. The system automatically obtains circuit layout data, identifies existing vias, creates new via candidates, evaluates their impact on original connections, and determines which vias to keep. This automation resolves the complexity issue by making the process systematic and self-executing.
2Productivity
If multiple new vias are created to ensure electrical connectivity, then the yield of functional chips is improved, but the manufacturing process time increases
Solution Approach 1:
The patent applies preliminary action by performing via creation and evaluation during the design phase rather than during manufacturing. The system automatically generates and evaluates via candidates before production, so that when manufacturing occurs, the via locations are already determined. This shifts the time investment to the design phase, where automation can efficiently handle the computational work without impacting manufacturing throughput.
Solution Approach 2:
The patent replaces manual via creation processes with an automated computer-based system. Instead of engineers manually analyzing layouts and creating via candidates, the system automatically obtains circuit layout data, identifies existing vias, generates new via candidates, and evaluates their impact. This substitution of mechanical/manual processes with automated computational processes significantly reduces the time required for via creation while maintaining high yield.
3Reliability
If new vias are added to compensate for manufacturing defects, then the electrical connection success rate is improved, but the design and manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by creating and evaluating via candidates during the design phase, before manufacturing begins. The system identifies existing vias, creates new via candidates around them, and evaluates whether these candidates would disrupt original circuit connections. By performing this analysis in advance, the patent prepares a robust via layout that compensates for potential manufacturing defects without adding complexity during the actual manufacturing process.
Solution Approach 2:
The patent implements self-service through an automated evaluation process that determines which new vias to keep based on their impact on original connections. The system automatically evaluates each via candidate and makes decisions about retention without human intervention. This self-service approach handles the design complexity internally, presenting a finalized via layout to manufacturers without requiring them to understand or manage the complexity of via selection and evaluation.
Data Source
AI summary
A method for creating new vias in an integrated circuit chip. The method automatically creates a plurality of new vias around an original via for electrically connecting two metal layers to each other in circuit layout data of the integrated circuit chip. The new vias also electrically connect the two metal layers to each other. According to the new vias, the probability of certainly electrically connecting the two metal layers of the integrated circuit chip to each other can be increased when the integrated circuit chip is being manufactured.


