Through Substrate Via Formation in Integrated Circuits
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Solution Overview
Problem
Current methods for forming through substrate vias in integrated circuit chips face challenges such as high mechanical stress, limited miniaturization of via width, and increased wafer brittleness, which restrict the achievement of high form factor vias and efficient component density.
Innovation Solution
A method involving the formation of openings in a first semiconductor wafer, filling them with conductive material, bonding a second wafer with an insulating layer to the first, and creating vias from the second wafer's rear surface to reach the conductive material, allowing for thinning of the first wafer to achieve vias with widths less than 1 μm and maintaining mechanical integrity without a temporary handle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the wafer thickness is reduced to enable smaller via widths, then the form factor of vias is improved, but the mechanical stress and brittleness of the wafer increase
Solution Approach 1:
The wafer fabrication process is segmented into two independent stages: first forming shallow openings and filling them with conductive material in a thick wafer, then bonding a thin wafer to achieve final thinning. This segmentation allows each stage to be optimized independently - the thick wafer provides mechanical support during opening formation, while the final thin wafer achieves the desired form factor.
Solution Approach 2:
The conductive material is preliminarily deposited in shallow openings (depth < 10 μm) before the wafer thinning process. This preliminary action allows the conductive structures to be formed when the wafer still has sufficient mechanical strength, avoiding the need to manipulate extremely thin wafers during complex via formation processes.
2Manufacturing precision
If high temperatures are used for conformal deposition of conductive material, then the deposition quality is improved, but the glue bonding the wafer to the temporary handle deteriorates
Solution Approach 1:
The conductive material is preliminarily deposited in shallow openings before wafer bonding, when the wafer still has sufficient mechanical strength. This eliminates the need for high-temperature conformal deposition in extremely thin wafers, and removes the constraint of glue temperature limits since no temporary handle bonding is required in the final process.
Solution Approach 2:
The temporary handle and its associated glue bonding step are completely removed from the process. This extraction eliminates the temperature constraint imposed by glue degradation, allowing flexible temperature selection for conductive material deposition based solely on material requirements.
3Productivity
If the wafer is thinned to achieve smaller via widths, then the component density is improved, but the difficulty of manipulating the wafer increases
Solution Approach 1:
The process segments wafer manipulation into two phases: handling thick wafers (easy to manipulate) during opening formation and conductive material deposition, then handling the final thin structure after bonding. This segmentation ensures that complex operations are performed when mechanical strength is sufficient.
Solution Approach 2:
All difficult operations (opening formation, conductive material deposition) are performed preliminarily while the wafer structure is still mechanically robust. The final thinning and bonding steps create the high-density structure without requiring manipulation of extremely thin wafers during sensitive processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of integrated circuits with extremely thin wafers and high form factor vias, reducing mechanical stress and parasitic electric couplings, while allowing for efficient thermal dissipation and improved component performance without the need for gluing or temporary handles.
Implementation Method 1
filling them with a conductive material
Implementation Method 2
covering with an insulating layer a front surface of a second semiconductor wafer
Implementation Method 3
bonding a second wafer with an insulating layer to the first
Data Source
AI summary
A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.