Direct Backside Source/Drain Contacts for Via-Free Power Routing
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Solution Overview
Problem
Conventional semiconductor manufacturing processes are complex and hinder size reduction and miniaturization due to the need for through vias from the backside to the frontside for connecting source/drain regions to backside power rails, which complicates the formation of efficient connections.
Innovation Solution
The implementation of direct backside contacts that self-align with the edges of input and output source/drain regions, allowing for efficient connections to backside power sources without the complexity of through vias, where input source/drain regions are connected to one direct backside contact and output regions to another, with the option of forming backside source/drain contacts on partial or entire surfaces and using vias when necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through vias are used to connect source/drain regions to backside power rails, then power connections are established, but manufacturing complexity increases and device size reduction is hindered
Solution Approach 1:
The patent transitions from vertical through-via connections to lateral surface contact connections. By forming source/drain contacts on the surface of the semiconductor substrate adjacent to the channel, the connection geometry changes from depth-oriented (vertical) to surface-oriented (lateral), eliminating the need for complex via formation while maintaining reliable power delivery.
Solution Approach 2:
The invention extracts and eliminates the through-via structure from the connection path. By directly contacting the source/drain regions through surface contacts, the intermediate via structure is removed entirely, simplifying the manufacturing process while preserving the essential function of power delivery to the active regions.
2Reliability
If through vias are used for backside connections, then power rails are connected to source/drain regions, but device miniaturization is impeded
Solution Approach 1:
The connection approach shifts from consuming vertical substrate depth (via length) to utilizing horizontal substrate surface area (contact area). This dimensional shift allows for more efficient space utilization, enabling device scaling as the connection footprint can be optimized in the lateral plane rather than being constrained by via depth requirements.
3Device complexity
If direct backside contacts are used, then manufacturing complexity is reduced and miniaturization is enabled, but connection efficiency must be maintained
Solution Approach 1:
The patent applies local quality by positioning contacts specifically at the source and drain regions where current entry/exit occurs. The contact geometry, material composition, and dimensional characteristics are locally optimized at these critical interfaces to ensure low resistance and high current carrying capacity, while the rest of the substrate maintains its simplified structure.
Data Source
AI summary
A semiconductor structure comprises a first transistor and a second transistor. The first transistor comprises a first input source/drain region and a first output source/drain region, and the second transistor comprises a second input source/drain region and a second output source/drain region. The first input source/drain region and the second input source/drain region are connected to a first source/drain contact, and the first output source/drain region and the second output source/drain region are connected to a second source/drain contact. The first source/drain contact and the second source/drain contact on a same side of the semiconductor structure.