Via Hole Formation in III-V Nitride Semiconductor Devices
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Solution Overview
Problem
Conventional methods for forming via holes in semiconductor devices with III-V nitride semiconductor layers on silicon carbide substrates face challenges in miniaturizing surface elements and speeding up the via hole process due to high aspect ratios and low etching rates, particularly with silicon carbide being difficult to etch.
Innovation Solution
A method involving selective dry-etching of the III-V nitride semiconductor layer from the surface side using a chlorine-based gas and the silicon carbide substrate from the back side using a fluorine-based gas, with specific etching conditions to achieve high selection ratios and prevent side etching, allowing for the formation of surface and back via holes that reduce aspect ratios and facilitate faster processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the diameter of via hole is reduced to miniaturize elements, then element size is reduced, but aspect ratio increases and via hole work time increases
Solution Approach 1:
The via hole formation process is segmented into two separate operations: first forming a surface via hole through the III-V nitride semiconductor layer, then forming a back via hole through the silicon carbide substrate. This segmentation allows each etching operation to work on a reduced depth, lowering the aspect ratio and etching time for each step while maintaining the overall miniaturization benefit.
Solution Approach 2:
The surface via hole is formed in advance before mounting the wafer to the support substrate. This preliminary action removes the need to etch through the entire thickness of the III-V nitride layer during the back-side etching process, thereby reducing the aspect ratio and etching time for the subsequent back via hole formation.
2Loss of time
If the diameter of via hole is increased to reduce aspect ratio, then via hole work time is reduced, but element size increases
Solution Approach 1:
The via hole formation is divided into two separate etching processes targeting different layers. The first process creates a surface via hole with small diameter through the thin III-V nitride layer, while the second process creates a back via hole with potentially larger diameter through the silicon carbide substrate. This segmentation decouples the diameter-size constraint from the aspect ratio-time constraint.
Solution Approach 2:
Different via hole diameters are applied to different locations and layers: the surface via hole has a small diameter suitable for miniaturized elements, while the back via hole can have a larger diameter optimized for etching speed and aspect ratio reduction. Each via hole is locally optimized for its specific function and layer.
3Manufacturing precision
If dry etching is used to etch silicon carbide, then via hole formation is achieved, but etching rate is low and via hole work takes long time
Solution Approach 1:
The etching process is segmented into two separate dry etching operations: one for the III-V nitride semiconductor layer and another for the silicon carbide substrate. By dividing the total etching depth into two manageable segments, each operation maintains a low aspect ratio, enabling the use of dry etching with acceptable etching rates while achieving precise via hole formation.
Solution Approach 2:
The surface via hole is formed in advance before wafer mounting, removing the need to etch through the III-V nitride layer during back-side processing. This preliminary action reduces the depth of the subsequent back via hole etching, improving etching speed and productivity while maintaining precision.
4Reliability
If via hole work is performed through the entire thickness, then complete penetration is achieved, but aspect ratio becomes large and process time increases
Solution Approach 1:
The via hole formation is segmented into two separate penetration processes: surface via hole formation through the III-V nitride layer, and back via hole formation through the silicon carbide substrate. Each segment achieves complete penetration through its respective layer with a manageable aspect ratio, ensuring reliability while reducing total process time.
Solution Approach 2:
The surface via hole is formed in advance as a preliminary action, creating an opening that guides subsequent back-side etching. This preliminary penetration ensures complete through-hole formation is achieved in two controlled steps rather than one lengthy process, maintaining reliability while reducing time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the miniaturization of surface elements and accelerates via hole work by maintaining a low aspect ratio and preventing side etching issues, ensuring efficient and controlled formation of semiconductor devices.
Implementation Method 1
a step of forming a surface via hole by selectively dry-etching the III-V nitride semiconductor layer from the surface side using a first gas
Implementation Method 2
a step of forming a back via hole which is to be connected to the surface via hole by selectively dry-etching the silicon carbide substrate from the back side using a second gas
Data Source
AI summary
An aluminum gallium nitride/gallium nitride layer (III-V nitride semiconductor layer) is formed on the surface of a silicone carbide substrate. The aluminum gallium nitride/gallium nitride layer is dry-etched from an exposed surface, using a chlorine-based gas (first gas) and a surface via hole is thereby formed. A back via hole, which is to be connected to the surface via hole, is formed by dry-etching the silicon carbide substrate from an exposed back side using a fluorine-based gas (second gas).