Semiconductor Via Hole Liner for Plating Quality
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Solution Overview
Problem
Conventional fan-out semiconductor packages face challenges in forming conductive vias due to the poor circularity and high surface roughness of via holes caused by differing laser absorbability of epoxy resin and SiO2 fillers, leading to complex and costly plating processes with potential voids in the conductive path.
Innovation Solution
A semiconductor device with a package body that includes a dielectric material with a smoother sidewall surface roughness, allowing for improved plating quality and reduced void formation by lining the via holes with a dielectric material before filling with conductive metal, which reduces the surface roughness and enhances adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If laser drilling is used to form via holes in the package body, then the via holes can be formed efficiently, but the circularity of the sidewall is poor and the surface roughness is high due to different laser absorbability of epoxy resin and SiO2 fillers
Solution Approach 1:
The patent applies a preliminary action by forming a via hole liner layer on the sidewall of the via hole before the plating process. This liner layer is deposited to cover the rough sidewall surface created by laser drilling, providing a smooth foundation for subsequent plating operations and eliminating the need for complex post-drilling corrections
Solution Approach 2:
The via hole liner layer acts as an intermediary between the rough via hole sidewall and the plating layer. It mediates the interaction by providing a uniform surface that facilitates proper plating adhesion and eliminates the harmful effect of the rough sidewall caused by differential laser absorbability of the package body materials
2Ease of manufacture
If sputtering process is used to plate the via hole, then plating material can be dispensed, but the fillers hinder complete and uniform application of the plating layer to the sidewall due to small particle sizes and filler protrusions
Solution Approach 1:
The patent performs a preliminary action by depositing the via hole liner layer before the sputtering plating process. This liner layer creates a smooth, filler-free surface that allows the sputtering process to deposit plating material uniformly without the interference of protruding fillers, ensuring complete coverage of the sidewall including undersides
Solution Approach 2:
The via hole liner layer serves as an intermediary surface between the sputtering plating material and the via hole sidewall. It eliminates the hindering effect of fillers by providing a continuous, smooth substrate that enables uniform plating deposition, solving the problem of incomplete plating on filler undersides
3Reliability
If plating time is increased to reduce incomplete plating and void formation, then plating quality improves, but cost increases and productivity decreases
Solution Approach 1:
The patent applies a preliminary action by forming the via hole liner layer that creates an optimal plating surface. This preparation eliminates the need for extended plating times because the liner provides uniform nucleation sites for plating material, enabling complete and defect-free plating to be achieved in standard processing times
Solution Approach 2:
The via hole liner layer acts as an intermediary that facilitates efficient plating deposition. By providing a smooth, uniform surface, it enables the plating process to achieve complete coverage and high reliability without requiring excessive plating time, thus maintaining productivity while ensuring quality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution results in improved manufacturability and functionality of semiconductor devices by reducing voids and increasing productivity while lowering costs, with a smoother sidewall surface facilitating better plating quality and reliability of the conductive vias.
Implementation Method 1
the package body of the package is drilled through the use of a laser to form at least one via hole therein
Implementation Method 2
A semiconductor device with a package body that includes a dielectric material with a smoother sidewall surface roughness, allowing for improved plating quality
Data Source
AI summary
In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package body via. The semiconductor chip includes a plurality of conductive pads. The package body encapsulates a sidewall of the semiconductor chip, and has at least one hole formed therein having a sidewall which is of a prescribed first surface roughness value. The through package body via is disposed in the hole of the package body and comprises a dielectric material and at least one conductive interconnection metal. The dielectric material is disposed on the sidewall of the hole and defines at least one bore having a sidewall which is of a second surface roughness value less than the first surface roughness value. The interconnection metal is disposed within the bore.