Via Insulation Oxidized Barrier Layer High Voltage Reliability

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Solution Overview

Problem

Modern integrated circuits face insulator field breakdown in vias under high voltage applications due to their vulnerability, despite dielectric and metallic liners being used.

Innovation Solution

A method involving depositing a dielectric layer, a barrier layer, allowing the barrier layer to oxidize, and then depositing a conducting layer within the via of a semiconductor substrate, using processes like CVD, PVD, and ALD, to create a robust structure that can withstand high voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dielectric and metallic liners are used in vias, then basic insulation is provided, but the vias remain vulnerable to insulator field breakdown under high voltage applications

Engineering Contradiction:
Improvevia insulation reliabilityVSAvoidinsulator field breakdown
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The via structure is segmented into multiple functional layers: a first dielectric layer for basic insulation, a barrier layer (tantalum or tungsten) for adhesion and diffusion barrier, and a second dielectric layer (silicon oxide) specifically for high voltage insulation. This segmentation allows each layer to address specific requirements, with the second dielectric layer providing enhanced breakdown voltage resistance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The via structure employs composite materials combining different dielectric properties and barrier characteristics. The combination of silicon-based dielectric, tantalum/tungsten barrier layer, and silicon oxide second dielectric layer creates a composite structure that leverages the advantages of each material: good adhesion from the barrier layer, basic insulation from the first dielectric, and high voltage resistance from the silicon oxide layer.

Inventive Principle:
Principle #40Composite materials

2Reliability

If multiple layers are deposited in the via, then insulation and high voltage resistance are improved, but the manufacturing process complexity increases

Engineering Contradiction:
Improvehigh voltage withstand capabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The barrier layer is deposited and oxidized beforehand to create a stable foundation before depositing the second dielectric layer. This preliminary action ensures proper adhesion and prevents contamination, reducing the need for additional corrective steps later in the manufacturing process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The manufacturing process utilizes parameter changes through oxidation (converting the barrier layer from metallic to oxide state) and controlled deposition conditions. These parameter changes enable the formation of distinct functional layers with specific properties, achieving high voltage resistance while maintaining a systematic manufacturing approach.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively insulates vias, enabling them to withstand high voltage applications and provides electrical connectivity between substrates, with the oxidized barrier layer adding a dielectric layer and forming a capacitor structure.

Implementation Method 1

allowing the barrier layer to oxidize

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

depositing, in the via, a dielectric layer

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Implementation Method 3

depositing, in the via, a conducting layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Data Source

PatentUS10079175B2Insulating a via in a semiconductor substrate
Publication Date: 2018.09.18 ADEIA SEMICONDUCTOR SOLUTIONS LLC
  • US10079175B2 patent drawing
  • US10079175B2 patent drawing
  • US10079175B2 patent drawing

AI summary

Insulating a via in a semiconductor substrate, including: depositing, in the via, a dielectric layer; depositing, in the via, a barrier layer; allowing the barrier layer to oxidize; and depositing, in the via, a conducting layer.