Conductive Via Insulator Structure for Parasitic Capacitance Reduction
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Solution Overview
Problem
Parasitic capacitance between conductive vias in integrated circuitry adversely affects circuit performance, leading to inefficiencies in memory cell operations due to high capacitance values exceeding 40 attofarads at low voltage deltas.
Innovation Solution
A method of forming a conductive via and integrated circuitry structure involving a conductive via and line with specific insulator materials and compositions, where first insulator material with a dielectric constant no greater than 4.0 is formed laterally outward of the conductive via, and second insulator material with a higher dielectric constant is formed outward of the first insulator, reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional conductive vias are placed laterally adjacent to each other, then circuit functionality is achieved, but parasitic capacitance increases to 40 attofarads or more
Solution Approach 1:
A first insulator material with dielectric constant k≤4.0 is introduced as an intermediary layer between laterally-adjacent conductive vias. This intermediate insulating layer reduces the parasitic capacitance coupling between adjacent vias from 40 attofarads or more to less than 30 attofarads, while still allowing the vias to perform their intended circuit connection functions.
Solution Approach 2:
The patent employs a composite insulator structure consisting of a first insulator material (k≤4.0) and a second insulator material (k>4.0) with different dielectric constants. The first insulator material is positioned between laterally-adjacent conductive vias to minimize parasitic capacitance, while the second insulator material is used in other regions where higher dielectric constant is beneficial for capacitance storage.
2Object-generated harmful factors
If first insulator material with k≤4.0 is formed laterally outward of conductive via, then parasitic capacitance is reduced to less than 30 attofarads, but manufacturing complexity increases
Solution Approach 1:
The first insulator material with low dielectric constant (k≤4.0) is selectively formed only in specific regions where parasitic capacitance reduction is critical—specifically, laterally outward from conductive vias that are laterally-adjacent to other vias. In regions where high capacitance storage is needed, the second insulator material with higher dielectric constant (k>4.0) is used instead. This localized application of different material properties reduces manufacturing complexity compared to using low-k material throughout the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach effectively minimizes parasitic capacitance to less than 30 attofarads at a voltage delta of no greater than 1.1 volts, enhancing circuit performance by reducing unwanted electrical interactions between conductive elements.
Implementation Method 1
first insulator material having k no greater than 4.0 is formed laterally outward of the conductive via
Implementation Method 2
second insulator material having k greater than 4.0 is formed laterally outward of the first insulator
Data Source
AI summary
A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically coupled to and crossing above the conductive via. The conductive line comprises first conductive material and the conductive via comprises second conductive material of different composition from that of the first conductive material. The conductive line and the conductive via respectively having opposing sides in a vertical cross-section. First insulator material having k no greater than 4.0 is formed laterally outward of the opposing sides of the second conductive material of the conductive via selectively relative to the first conductive material of the opposing sides of the conductive line. The first insulator material is formed to a lateral thickness of at least 40 Angstroms in the vertical cross-section. Second insulator material having k greater than 4.0 is formed laterally outward of opposing sides of the first insulator material in the vertical cross-section. Additional method aspects, including structure independent of method of fabrication, are disclosed.