Via Pillar Substrates for Ultra Fine Pitch Flip Chip Interconnects

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Solution Overview

Problem

Current methods for fabricating high-density interconnects in IC substrates, such as drill & fill technology, face limitations in achieving small via diameters, varying via sizes, and precise geometries due to rough side walls and tapering, leading to reliability issues and increased costs, while also challenging the alignment and application of solder bumps for flip chip technology.

Innovation Solution

The development of a multilayer composite electronic structure with via posts embedded in a dielectric, where copper vias are electroplated and capped with solderable materials, allowing for precise alignment and deposition of micro bumps compatible with chip bumps, using pattern plating and panel plating methodologies to create high-density, small-pitch interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If laser drilling is used to create via channels, then via channels can be formed through dielectric material, but the side walls become rough and tapered, reducing effective diameter and causing reliability issues

Engineering Contradiction:
Improvevia channel formationVSAvoidvia wall smoothness and cylindrical shape
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent replaces the mechanical laser drilling process with an electrochemical etching process using ferric chloride solution. This chemical etching method produces smooth, non-tapered via walls by uniformly removing dielectric material through electrochemical reactions, eliminating the roughness and tapering problems inherent in mechanical laser drilling while maintaining ease of manufacture for high-density via arrays.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the fundamental parameter of via formation from mechanical removal (laser drilling) to electrochemical removal (ferric chloride etching). This parameter change transforms the via wall characteristics from rough and tapered to smooth and cylindrical, directly resolving the manufacturing precision issue while preserving the ability to efficiently create high-density via patterns.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If electroplating is used to fill drilled via holes, then via channels can be filled with copper, but dimpling or overfill occurs, creating difficulties for subsequent via stacking

Engineering Contradiction:
Improvevia fillingVSAvoidvia fill uniformity and surface flatness
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by creating a precise copper seed layer pattern through photolithography and electroplating before the via filling process. This pre-formed seed layer acts as a controlled template that guides subsequent copper deposition, ensuring uniform via filling without dimpling or overfill. The preliminary seed layer pattern prevents the electroplating process from creating surface irregularities that would interfere with subsequent via stacking operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a copper seed layer as an intermediary between the dielectric substrate and the final via fill. This intermediate layer serves as a controlled foundation that regulates copper deposition during electroplating, preventing direct uncontrolled growth that causes dimpling and overfill. The seed layer mediates the filling process to achieve uniform via structures suitable for high-density stacking.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If drill & fill technology is used to create high-density vias, then interconnects can be formed, but the process becomes expensive and time-consuming due to separate drilling of each via

Engineering Contradiction:
Improvevia density and geometry controlVSAvoidfabrication throughput rate
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent merges multiple separate via drilling operations into a single batch chemical etching process. Instead of drilling each via individually with a laser (sequential operation), the ferric chloride etching solution simultaneously processes entire arrays of vias across the substrate in parallel (batch operation). This merging of operations dramatically increases productivity while maintaining precise control over via density and geometry through the uniform chemical etching process.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent replaces the mechanical sequential laser drilling system with a chemical batch etching system using ferric chloride. This substitution transforms the production methodology from a time-consuming sequential mechanical process to an efficient parallel chemical process, dramatically improving throughput while maintaining the ability to create high-density via patterns with precise geometric control.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

4Adaptability or versatility

If different sized via channels are drilled and filled, then varied geometries can be achieved, but the filling rates differ, exacerbating dimpling or overfill problems

Engineering Contradiction:
Improvevia size variationVSAvoidvia fill consistency across different sizes
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating spatially varying copper seed layer thicknesses or compositions tailored to specific via locations and sizes. Different regions of the substrate receive customized seed layer characteristics that are optimized for their local via geometry requirements. This localized customization of the seed layer ensures that subsequent electroplating fills via of different sizes at appropriate rates, preventing dimpling in smaller vias and overfill in larger vias, thereby achieving consistent fill quality across varied via geometries.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes parameters of the seed layer (such as thickness, composition, or deposition conditions) locally across the substrate to match the specific requirements of different via sizes. By adjusting seed layer parameters rather than via fill parameters, the process achieves uniform filling across varied via geometries, as the seed layer acts as a pre-configured template that guides appropriate copper deposition rates for each local via configuration.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of substrates with higher via densities and varied geometries, improving reliability and reducing costs by enabling precise alignment and efficient solder bump application, thus enhancing the miniaturization and complexity of electronic components.

Implementation Method 1

The filling process of the drilled via holes is usually achieved by copper electroplating.

Methodology Applied
Scientific EffectElectroplating: Electroplating

Implementation Method 2

one widely implemented manufacturing technique that creates interconnecting vias between layers uses lasers to drill holes through the subsequently laid down dielectric substrate

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS10779417B2Substrates with ultra fine pitch flip chip bumps
Publication Date: 2020.09.15 ZHUHAI ACCESS SEMICONDUCTOR CO LTD
  • US10779417B2 patent drawing
  • US10779417B2 patent drawing
  • US10779417B2 patent drawing

AI summary

A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder.