Via Plug Contact Area Reduction Semiconductor Resistance

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Solution Overview

Problem

Current semiconductor devices face challenges in reducing size and weight while maintaining effective electrical connections, leading to increased contact resistance due to limited contact areas between via plugs and pad structures.

Innovation Solution

The semiconductor device incorporates a via plug that passes through multiple layers, including insulating and substrate layers, with a conductive pattern that provides a larger contact area and direct contact with both upper and lower pad structures, utilizing a via conductive layer and core pattern to reduce electrical contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If semiconductor device size is reduced to meet miniaturization requirements, then device footprint decreases, but via plug contact area with pad structures becomes even more limited, exacerbating contact resistance

Engineering Contradiction:
Improvedevice footprintVSAvoidcontact resistance
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent resolves the miniaturization conflict by exploiting the vertical dimension. While the horizontal footprint is reduced, the via plug is designed to contact multiple pad conductive layers at different vertical levels. This vertical stacking of contact points compensates for the reduced horizontal contact area, maintaining low contact resistance even in compact device configurations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The via plug structure is designed to nest within the vertical space between different pad conductive layers. Multiple pad conductive layers are positioned at different heights, and the via plug contacts these nested layers sequentially or simultaneously. This nesting approach maximizes the use of vertical space to increase contact area without increasing the horizontal device footprint.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS10658413B2Semiconductor device including via plug
Publication Date: 2020.05.19 SAMSUNG ELECTRONICS CO LTD
  • US10658413B2 patent drawing
  • US10658413B2 patent drawing
  • US10658413B2 patent drawing

AI summary

A semiconductor device includes a lower insulating layer on a lower substrate, a lower pad structure inside the lower insulating layer, an upper insulating layer on the lower insulating layer, an upper pad structure inside the upper insulating layer, and an upper substrate on the upper insulating layer. A via plug passes through at least a portion of each of the upper substrate, the upper insulating layer, and the lower insulating layer, and in contact with the upper pad structure and the lower pad structure. The upper pad structure includes upper pad conductive layers and an upper connection layer between the upper pad conductive layers. The upper connection layer includes a conductive pattern having a shape different from a shape of at least one of the upper pad conductive layers. The via plug is in direct contact with the upper pad conductive layers and the upper connection layer.