Via Resistance Reduction Using Self-Assembled Monolayer in Semiconductor Devices
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Solution Overview
Problem
As semiconductor devices are scaled down, via resistance increases due to the deposition of barrier and liner layers, making it challenging to achieve efficient electrical connections, and existing metallization techniques are prone to errors and residue issues.
Innovation Solution
A method involving the formation of a self-assembled monolayer (SAM) and a sacrificial layer within vias, where the SAM has a greater thickness at the bottom than the sidewalls, allowing for selective deposition and removal processes to avoid barrier layers at the via bottom, enabling direct electrical connection between conductive layers without intermediate barriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier and liner layers are deposited in vias during scaling down, then via resistance increases, but electrical connection efficiency deteriorates
Solution Approach 1:
The patent applies local quality by making the SAM layer thickness non-uniform across different locations within the via. The SAM layer is thicker at the bottom of the via and thinner at the sidewalls, allowing selective removal processes to differentially treat different regions. This local variation in thickness enables the bottom SAM layer to protect against barrier layer deposition while sidewall SAM layers can be removed to allow proper barrier layer formation, thus resolving the contradiction between maintaining low via resistance and ensuring reliable electrical connections.
2Ease of manufacture
If existing metallization techniques are used, then manufacturing process is simpler, but error and residue issues increase
Solution Approach 1:
The patent employs preliminary action by pre-forming the self-assembled monolayer (SAM) layer throughout the via structure before any barrier layer deposition. This SAM layer serves as a protective precursor that prevents unwanted barrier material from depositing on the via bottom. The sacrificial layer is then used to selectively remove the bottom SAM layer at a controlled stage, ensuring clean via bottoms free of barrier residues before final conductive material deposition. This preliminary protective action eliminates the need for complex post-deposition cleaning processes and reduces manufacturing errors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces via resistance by eliminating barrier layers at the via bottom, enhancing electrical conductivity and mechanical connection, thus improving the performance and efficiency of semiconductor devices as they are miniaturized.
Implementation Method 1
forming a self-assembled monolayer (SAM) over the insulating layer, a sidewall of the via, and a bottom of the via
Data Source
AI summary
In a method of making a semiconductor device, the method includes: forming a first conductive layer over a substrate; forming an insulating layer on the first conductive layer; forming a via through the insulating layer to expose the first conductive layer; forming a self-assembled monolayer (SAM) over a bottom of the via; forming a barrier layer at a sidewall of the via; removing the SAM over the bottom of the via; and forming a second conductive layer over the barrier layer and the bottom of the via such that the first conductive layer is electrically connected to the second conductive layer without the barrier layer between the first conductive layer and the second conductive layer at the bottom of the via.