Via Formation with Self-Aligned Etching for Semiconductor Interconnects
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Solution Overview
Problem
Current methods for forming vias in semiconductor devices face challenges in achieving perfect alignment, leading to overlay errors and via-induced-metal-bridge (VIMB) defects, especially as interconnect spacing sizes shrink, which exacerbates time-dependent dielectric breakdown (TDDB) issues.
Innovation Solution
A method involving the formation of a semiconductor device that includes a series of etching processes and the use of a hard mask layer to create vias with specific dimensions and orientations, ensuring precise alignment and reducing the risk of bridging between interconnect lines by maintaining tapered profiles and controlled critical dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via sizes are increased to ensure reliable electrical connections, then connection reliability is improved, but overlay errors increase leading to VIMB defects
Solution Approach 1:
The via formation process is segmented into multiple etching steps (first etching process and second etching process) with different purposes. The first etching process forms an initial via opening, while the second etching process performs self-aligned widening that automatically compensates for overlay errors. This segmentation allows the via to achieve both sufficient size for reliable connection and precise alignment through the self-aligned nature of the process steps.
Solution Approach 2:
The first etching process performs a preliminary action by forming an initial via opening that serves as a template for the subsequent self-aligned etching. This preliminary structure enables the second etching process to automatically widen the via in a controlled manner that maintains alignment with the underlying interconnect, thereby preventing VIMB defects while ensuring adequate via size for reliable electrical connection.
2Productivity
If interconnect spacing size is reduced to increase functional density, then chip area utilization is improved, but TDDB problems worsen
Solution Approach 1:
The via width is made non-uniform through the self-aligned etching process, creating local quality variations. The via is wider at the top and narrower at the bottom, which concentrates the electrical stress in the lower region where the dielectric is thinnest and most vulnerable to TDDB. This local quality adjustment allows reduced interconnect spacing while maintaining overall reliability by protecting the critical lower via region.
Solution Approach 2:
The via dimensional parameters are changed through the self-aligned etching process, which automatically adjusts the via width profile based on the underlying interconnect geometry. This parameter change creates a via shape that adapts to the reduced interconnect spacing, maintaining adequate electrical performance while minimizing the impact on surrounding dielectric structures and reducing TDDB susceptibility.
3Manufacturing precision
If self-aligned dual etching process is used to reduce overlay errors, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The self-aligned dual etching process employs self-service mechanisms where the previously formed via opening and interconnect structures automatically serve as alignment references for subsequent etching steps. The process uses the existing via opening as a mask and template, eliminating the need for separate alignment operations or additional mask layers. This self-service approach achieves high manufacturing precision while minimizing the increase in process complexity by leveraging existing structures rather than adding independent alignment systems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces overlay errors and VIMB defects, improving the reliability of semiconductor devices by ensuring accurate alignment and minimizing electrical shorts, while also addressing TDDB issues associated with shrinking interconnect spacing sizes.
Implementation Method 1
performing a first etching process on the semiconductor device to extend the second opening into the dielectric layer to form an extended second opening
Data Source
AI summary
The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.