Via Formation Using Sidewall Image Transfer for Lateral Dimension Control
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Solution Overview
Problem
In semiconductor processing, it is challenging to control the lateral dimensions of vias during fabrication, particularly in self-aligned via processing, where the critical dimension control is not maintained outside the hard mask, leading to improper via dimensions and aspect ratio issues, which can result in elongated via structures.
Innovation Solution
A method employing a sidewall image transfer process to form pillars that define the lateral dimensions of vias in both directions, using a mandrel and spacer layers, where the pillars act as a hard mask to etch the dielectric layer and ensure bi-directional control of via openings, allowing for precise via formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If self-aligned via processing is used to simplify via formation, then via alignment is improved, but lateral dimension control deteriorates
Solution Approach 1:
The patent segments the via formation process into distinct stages: first forming mandrels with initial dimensions, then depositing spacer material around the mandrels to define the final via dimensions. This segmentation allows independent control of alignment (through mandrel placement) and lateral dimensions (through spacer thickness), resolving the contradiction between ease of alignment and precision of dimension control.
Solution Approach 2:
The patent introduces mandrels as intermediary structures that temporarily define the via location and are later removed. These mandrels serve as mediators between the lithography process and the final via formation, enabling precise lateral dimension control through the spacer-mandrel interaction while maintaining simple alignment procedures.
2Ease of manufacture
If conventional hard mask patterning is used, then via formation is simplified, but critical dimension control in multiple directions deteriorates
Solution Approach 1:
The patent applies local quality by making the spacer material thickness the controlling factor for via critical dimensions in directions where conventional hard masks fail. The spacer's uniform thickness provides precise lateral dimension control specifically at the via locations, while the overall process remains simplified through the self-aligned nature of spacer deposition around mandrels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides improved critical dimension control and aspect ratio management, resulting in accurately formed vias with controlled lateral dimensions, reducing the risk of device shorting and maintaining effective interconnect resistance and capacitance, while advancing miniaturization efforts in semiconductor devices.
Implementation Method 1
a spacer layer 126 of a spacer material is formed over the mandrel 120
Implementation Method 2
a spacer layer 126 of a spacer material is formed over the mandrel 120
Implementation Method 3
The mandrel 120 is then removed to release the pillar 110, 210
Implementation Method 4
etching a via opening in the dielectric layer using the via mask
Data Source
AI summary
A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.