Through Via Solder Bump Alignment via Blind Hole Filling
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Solution Overview
Problem
Current technologies for manufacturing through vias in Multi-Chip Modules (MCMs) are limited by the large size of solder bumps, which restricts the miniaturization of electronic systems and complicates routing due to the need for wide chip surfaces and complex interposer layers, especially when dealing with diverse memory and processing units.
Innovation Solution
A method for manufacturing solder bumps by forming blind holes in a substrate, filling them with conductive filler, and removing substrate portions to expose the solder material, allowing the bumps to protrude and align with through vias, thereby achieving smaller bump diameters comparable to the vias themselves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional solder bumps are used for through vias, then reliable electrical connection is achieved, but the bump size is large which limits miniaturization and increases routing complexity
Solution Approach 1:
The patent merges the formation of through vias and solder bumps into a single integrated process. The blind holes are formed first, then filled with conductive material that becomes both the via filler and the solder bump material. After removing the substrate from the back, the protruding conductive material forms the solder bump, eliminating the need for separate bump formation steps and reducing overall complexity.
Solution Approach 2:
The patent performs preliminary actions by pre-forming blind holes to the exact depth and diameter required, and pre-filling them with conductive material before substrate removal. This preliminary preparation ensures that when the substrate is removed, the solder bumps are already formed with precise dimensions and are perfectly aligned with the through vias, eliminating the need for subsequent alignment operations.
2Area of stationary object
If larger solder bumps are used, then easier alignment and connection is achieved, but chip surface area is wasted and miniaturization is restricted
Solution Approach 1:
The patent applies local quality by making the solder bump diameter equal to the via diameter, creating a localized precise structure only where needed. The conductive material is filled precisely to the depth of the blind hole, ensuring that the bump diameter matches the via diameter exactly, thus optimizing chip surface area usage without compromising connection reliability.
3Device complexity
If through vias are implemented without interposer layers, then routing is simplified, but alignment precision between chips is more critical
Solution Approach 1:
The patent merges the via formation and bump formation into a single integrated structure. The conductive material that fills the blind hole continues uninterrupted to form the protruding bump, creating a seamless transition from via to bump. This integration ensures perfect alignment between the via and bump, eliminating misalignment issues that would arise from separate formation processes.
Solution Approach 2:
The patent performs preliminary action by pre-forming the blind holes and pre-filling them with conductive material before substrate removal. This preliminary preparation ensures that the solder bumps are already formed with precise dimensions and are perfectly aligned with the through vias, eliminating the need for subsequent alignment operations and reducing sensitivity to alignment errors during chip stacking.
Data Source
AI summary
A substrate has a first surface and a second surface opposed to each other. A blind hole is formed in the substrate extending from the first surface at a location for each through via. Each blind hole is filled with a conductive filler; a deepest part of each filler forming a bump portion made of a solder material. Part of the substrate extending from the second surface is removed to have at least the bump portions protrude from the substrate. The non-protruding part of each filler defines the corresponding via and the bump portion defines the corresponding solder bump.