Video Encoding Decoding Parallel Processor Load Balancing
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Solution Overview
Problem
Existing video encoding and decoding systems face inefficiencies in parallel processing due to interdependency of video blocks, insufficient processor numbers, and memory bandwidth/latency issues, particularly in block-based compression standards like MPEG, which can lead to errors and reduced throughput.
Innovation Solution
The use of a Sequential Processor Array (SPA) and a Parallel Processor Array (PPA) interconnected by a high-speed data bus, where the SPA handles sequential instructions and the PPA processes parallel tasks, employing methods like Parallel Variable Length Decode (PVLD) and Parallel Block Decode (PBD) to enhance processing efficiency and error resilience.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If block-based video compression standards (MPEG, H.264, VC1) are used to compress video data, then video compression efficiency is improved, but parallel processing difficulty increases due to interdependency of bits or blocks
Solution Approach 1:
The patent divides the video frame into multiple slices, where each slice contains a set of blocks that can be decoded independently without requiring information from other slices. This segmentation breaks the interdependency between blocks, enabling parallel processing of different slices while maintaining the compression efficiency of block-based standards.
2Productivity
If multiple sequential processors are used to decode video data, then processing power increases, but memory bandwidth and latency become bottlenecks
Solution Approach 1:
The patent transitions from a purely sequential processing model to a hybrid model that introduces spatial parallelism through multiple processors working on different slices simultaneously. This dimensional change in processing architecture allows the system to overcome memory bandwidth limitations by distributing the memory access load across multiple processors rather than concentrating it on a single sequential processor.
3Reliability
If predictors are reset at each slice to improve error resilience, then error recovery capability is improved, but compression efficiency decreases
Solution Approach 1:
The patent implements slice-based segmentation where predictors are reset at slice boundaries, creating independent decoding units that can recover from errors without affecting other slices. This segmentation approach balances error resilience with compression efficiency by limiting the scope of predictor resets to only where necessary (at slice boundaries) rather than throughout the entire frame.
4Productivity
If all processors are kept busy to maximize performance, then processing throughput is improved, but load balancing difficulty increases due to differing processor requirements
Solution Approach 1:
The patent segments the video data into slices that can be independently assigned to different processors, simplifying load balancing. Each processor can work on a specific slice without requiring complex coordination with other processors, as the slice structure ensures that processors have independent work units with well-defined dependencies only on reference frames, not on each other's processing state.
Data Source
AI summary
A method is disclosed for the decoding and encoding of a block-based video bit-stream such as MPEG2, H.264-AVC, VC1, or VP6 using a system containing one or more high speed sequential processors, a homogenous array of software configurable general purpose parallel processors, and a high speed memory system to transfer data between processors or processor sets. This disclosure includes a method for load balancing between the two sets of processors.