Virtual-Bit FEC Data Processing for Ethernet Clock Synchronization
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Solution Overview
Problem
Existing Ethernet network solutions face complexity and high jitter issues in clock extraction and synchronization due to the implementation of Phase Locked Loop (PLL) circuits for Clock and Data Recovery (CDR), which complicates frame and inner codeword synchronization.
Innovation Solution
A data processing method involving first and second FEC encoding with periodic insertion and deletion of virtual bits to simplify clock extraction and synchronization, ensuring the baud rate of modulated symbol streams is an integer multiple of the Ethernet common reference clock frequency, thereby reducing PLL complexity and jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If PLL-based clock and data recovery is performed to extract clock from data and remove jitter, then clock synchronization is achieved, but the implementation complexity of the PLL circuit is high and the PLL jitter is high
Solution Approach 1:
The patent applies preliminary action by pre-processing the data stream before modulation to ensure the baud rate is an integer multiple of the reference clock frequency. This is achieved by adjusting the coding scheme and adding dummy bits if necessary, so that when data is transmitted and received, the clock extraction becomes straightforward without requiring complex PLL circuits. The clock frequency is predetermined based on the baud rate relationship, eliminating the need for complex jitter removal.
Solution Approach 2:
The patent changes the parameter relationship between baud rate and reference clock frequency to establish an integer multiple relationship. By controlling the baud rate to be exactly 2.5 times (or other integer multiple) the reference clock frequency, the system enables simple clock multiplication rather than complex PLL-based clock recovery. This parameter adjustment fundamentally simplifies the clock extraction mechanism while maintaining synchronization reliability.
2Reliability
If PLL-based clock and data recovery is performed to achieve clock extraction, then phase locking is achieved, but the jitter in the PLL output is high
Solution Approach 1:
The system performs preliminary configuration of the transmission parameters to ensure the baud rate is an integer multiple of the reference clock frequency. This pre-establishes a deterministic relationship between the transmitted signal and the receiver's reference clock, allowing the receiver to generate the exact same clock frequency through simple multiplication without relying on PLL feedback loops that introduce jitter.
Solution Approach 2:
The patent extracts and removes the problematic PLL component from the clock recovery system. By designing the transmission protocol to inherently provide clock information through the baud rate relationship, the system eliminates the need for PLL-based jitter removal, thereby removing the source of PLL jitter from the system.
3Ease of manufacture
If conventional FEC encoding is performed without virtual bit insertion, then data transmission is straightforward, but the baud rate is not an integer multiple of the reference clock frequency, complicating clock extraction
Solution Approach 1:
The patent introduces virtual bits as an intermediary element between the data encoding and transmission processes. These virtual bits act as a bridge that adjusts the data stream length to satisfy the integer multiple relationship with the reference clock frequency. The virtual bits are strategically inserted to ensure the total bit count after encoding results in a baud rate that is an exact integer multiple of the reference clock, thereby simplifying clock extraction without complicating the overall transmission system.
Data Source
AI summary
A data processing method and a data processing apparatus. First, W virtual bits are periodically inserted into a first data stream obtained through first FEC encoding to obtain a second data stream, where each second data stream includes at least one first bit sequence, the first bit sequence includes L=P+W bits, the P bits are from the first data stream, and the W bits are padded virtual bits. Then, second FEC encoding is performed on the second data stream to obtain a third data stream, where a second bit sequence is obtained by performing second FEC encoding on each first bit sequence, and the second bit sequence includes b codewords. Next, W virtual bits in each second bit sequence of the third data stream are deleted to obtain a fourth data stream. Then, processing including modulation is performed on m fourth data streams to obtain Y modulated symbol streams.