Virtual Clock for Media Synchronization
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Solution Overview
Problem
In digital multimedia playback systems, synchronizing media across multiple destinations while minimizing resource usage and network bandwidth, and mitigating packet losses in wireless networks to ensure uninterrupted playback is challenging, especially when different media components follow different network paths.
Innovation Solution
A method for indirectly measuring the rendering clock by computing a virtual clock using media data block size, number of blocks, and CPU clock increments, allowing for adjustments to synchronize media playback across multiple devices without specialized hardware, using a CPU and media rendering subsystem with separate clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If indirect clock measuring is used to synchronize media playback across multiple devices, then synchronization accuracy is improved, but device complexity increases due to virtual clock computation requirements
Solution Approach 1:
The patent introduces a virtual clock as an intermediary mechanism that mediates between the CPU clock domain and the media rendering clock domain. This virtual clock is computed indirectly through measuring media data block transfer timing, allowing synchronization without direct access to the rendering clock hardware, thus resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The patent replaces direct hardware clock measurement (mechanical/system-level access to rendering clock) with a software-based computational approach. By substituting the physical clock measurement mechanism with a virtual clock computed from data block timing information, the system achieves synchronization accuracy without increasing hardware complexity
2Reliability
If separate clock domains are used in CPU and media rendering subsystem, then playback reliability is improved through independent clock sources, but measurement precision deteriorates due to inability to directly access rendering clock
Solution Approach 1:
The patent transitions from directly measuring time in the rendering clock domain to measuring data block transfer events that bridge both clock domains. By observing the timing of media data blocks from the CPU's perspective (another dimension), the system can infer rendering clock characteristics without directly accessing it, maintaining both reliability and measurement precision
Solution Approach 2:
The patent implements a feedback mechanism where the system continuously monitors the timing of media data block transfers and uses this information to compute and adjust the virtual clock. This feedback loop allows the system to maintain accurate synchronization measurements despite the separation of clock domains, as the virtual clock is continuously refined based on observed transfer timing
3Quantity of substance
If virtual clock computation is performed using media data block timing, then resource usage is minimized without specialized hardware, but productivity decreases due to computational overhead
Solution Approach 1:
The patent makes the media rendering subsystem serve its own timing measurement needs by using its own data block transfer events to generate the timing information required for virtual clock computation. This self-service approach eliminates the need for separate specialized hardware or external measurement systems, minimizing resource usage while maintaining measurement accuracy
Solution Approach 2:
The patent makes the existing media data block transfer mechanism serve multiple functions: both its original purpose of delivering media data and the additional function of providing timing information for clock synchronization. This multi-functionality reduces the need for separate resources dedicated solely to timing measurement, thereby minimizing overall resource usage while maintaining productivity
Data Source
AI summary
A method for indirectly measuring the clock rate of a media rendering subsystem, in a media rendering device that has a separate hardware clock for rendering the media, by using the rate at which data requests are made of the CPU in the media rendering device and using the CPU clock to provide additional accuracy in measuring the clock rate.