Virtual FPGA Logic Analyzer Bandwidth Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional logic analysis in emulation environments for complex integrated circuits is inefficient due to the high bandwidth requirements for transferring signals between multiple field-programmable gate arrays (FPGAs), especially in advanced processes like 22 nm and below, where billions of logic circuits and signals are involved.
Innovation Solution
The implementation of a bandwidth-efficient emulation environment that uses virtual FPGAs within a system FPGA to emulate sections of the design under test (DUT), allowing the logic analyzer to obtain signals directly from virtual FPGAs instead of design FPGAs, thereby reducing the number of signals traced and exchanged between FPGAs, and optimizing communication bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional logic analysis is used to emulate complex DUTs with billions of logic circuits, then complete signal tracing capability is achieved, but communication bandwidth consumption increases significantly
Solution Approach 1:
The system segments the DUT into multiple partitions, with each partition emulated by a dedicated FPGA. Virtual FPGAs are created within the system FPGA to represent specific partitions, allowing the logic analyzer to selectively trace signals from only those partitions of interest rather than all signals across the entire DUT, thereby reducing bandwidth consumption while maintaining complete tracing capability for selected segments.
Solution Approach 2:
Virtual FPGAs act as intermediary components between the physical FPGAs and the logic analyzer. The virtual FPGAs within the system FPGA capture and present signals from multiple physical FPGAs, enabling the logic analyzer to obtain signals directly from the virtual FPGAs without requiring direct connections to all physical FPGAs, thus reducing communication bandwidth requirements.
2Measurement precision
If signals are traced from all design FPGAs to ensure complete analysis coverage, then analysis comprehensiveness is improved, but the number of signals exchanged between FPGAs increases
Solution Approach 1:
The system FPGA performs multiple functions by hosting both the logic analyzer and virtual FPGAs. The virtual FPGAs within the system FPGA can represent multiple physical FPGAs simultaneously, allowing a single system FPGA to provide signal tracing capabilities for the entire DUT while the logic analyzer traces signals from the virtual FPGAs, reducing the total number of signal exchanges required.
3Measurement precision
If direct signal tracing from design FPGAs is implemented, then signal acquisition accuracy is maintained, but hardware complexity increases
Solution Approach 1:
Virtual FPGAs create virtual copies of the signal interfaces from physical FPGAs within the system FPGA. These virtual copies present the same signal characteristics and interfaces as the physical FPGAs would, allowing the logic analyzer to acquire signals with the same accuracy as direct tracing while reducing hardware complexity by consolidating the tracing function within the system FPGA rather than requiring direct connections to all physical FPGAs.
Data Source
AI summary
An emulation environment includes a host system and an emulator. The host system configures the emulator to load a design under test (DUT) and the emulator emulates the DUT. The emulator includes one or more design field-programmable gate arrays (FPGAs) that emulate the DUT. In addition, the emulator includes at least one system FPGA with a logic analyzer and multiple virtual FPGA. The virtual FPGAs emulate sections of the DUT. By the virtual FPGAs emulating sections of the DUT, the logic analyzer is able to obtain for performing logic analysis certain signals from the virtual FPGAs, rather than from the design FPGAs.