Virtual Ground Array Two-Bit Memory Cell Operation Window
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Two-bit per cell non-volatile flash memory (NVM) semiconductor devices face a narrow 'window of operation' and leakage current issues during conventional programming, erasing, and reading methods, which affect data storage efficiency and endurance.
Innovation Solution
The 'Turn-On-Mode' operation is introduced, which involves hole injection erasure to lower the initial voltage threshold of both bits, allowing for programming and reading with reduced voltage shifts and minimizing leakage current by applying reference voltages and bias voltages strategically across the memory cell array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional programming methods are used for two-bit per cell NVM semiconductor devices, then programming can be performed, but the window of operation becomes narrow and leakage current increases
Solution Approach 1:
The patent applies preliminary erasure to lower the initial threshold voltage of the non-programmed bit before programming the target bit. This preliminary action creates a larger voltage threshold difference, thereby increasing the window of operation and reducing the second bit effect that causes leakage current.
Solution Approach 2:
The patent changes the voltage threshold parameter of the non-programmed bit by applying erasure voltages before programming. This parameter change ensures that the non-programmed bit starts at a lower threshold voltage, which increases the operational window and reduces interference during reading operations.
2Measurement precision
If the threshold voltage difference between programmed and un-programmed states is increased, then discrimination between cell states improves, but the programming complexity increases
Solution Approach 1:
The patent segments the programming process into distinct phases: first erasing the non-programmed bit to a low threshold voltage, then programming only the target bit. This segmentation allows for better state discrimination while managing complexity through a structured, multi-step process rather than attempting complex single-step programming.
Solution Approach 2:
The patent performs preliminary erasure of the non-programmed bit before programming the target bit. This preliminary action establishes a clear baseline threshold voltage, making it easier to achieve good state discrimination during the subsequent programming step without requiring overly complex programming schemes.
3Reliability
If the initial voltage threshold of both bits is lowered through hole injection erasure, then the second bit window of operation increases, but additional erasing steps are required
Solution Approach 1:
The patent changes the initial threshold voltage parameter of both bits through hole injection erasure before programming. This parameter change increases the second bit window of operation, allowing for more robust reading and reduced interference. The additional erasure step is accepted as a trade-off for achieving reliable operation with larger margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases the second bit window of operation, enhancing data storage efficiency and endurance by reducing voltage shifts and leakage current, thereby improving the overall performance of two-bit NVM cells in virtual ground arrays.
Implementation Method 1
holes are induced to flow from the gate layer into the nitride layer by application of a gate voltage bias
Data Source
AI summary
A non-volatile VG memory array employing memory semiconductor cells capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in associating with at least one electrical insulating layer, such as an oxide, is disclosed. Bit lines of the memory array are capable of transmitting positive voltage to reach the source/drain regions of the memory cells of the array. A method that includes the hole injection erasure of the memory cells of the array that lowers the voltage threshold of the memory cells to a value lower than the initial voltage threshold of the cells is disclosed. The hole injection induced lower voltage threshold reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened. The programming and read steps reduce leakage current of the memory cells in the array.