Compact Virtual Ground Diffusion ROM Architecture

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Solution Overview

Problem

Traditional diffusion programmable ROM architectures face challenges with high power consumption due to subthreshold leakage, especially in high-density designs, where the source terminals are connected to ground, leading to unacceptably high power usage.

Innovation Solution

A compact shared source line and bit line architecture is introduced, where source and bit lines are shared between adjacent columns, reducing the number of dedicated lines and allowing for reduced sizing of source and drain terminals while maintaining reduced leakage through a virtual ground arrangement.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If source terminals are connected to ground in traditional diffusion programmable ROM, then cell size is reduced, but power consumption increases due to subthreshold leakage

Engineering Contradiction:

Improvecell sizeVSAvoidpower consumption

Core Design Contradiction:

Area of stationary objectVSLoss of energy

Solution Approach 1:

The patent merges the source lines of two adjacent columns into a single shared source line, reducing the total number of source lines from N to N/2. This merging reduces the overall circuit area while the shared source line can be selectively pulled to virtual ground potential to serve multiple columns, reducing subthreshold leakage power consumption compared to traditional ground connections.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a virtual ground mechanism as an intermediary between the source terminals and actual ground. The shared source line acts as a virtual ground that can be dynamically activated, allowing the source terminals to float at a higher potential during non-access periods, thereby reducing subthreshold leakage while still providing a reference potential when needed.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of energy

If separate source lines are implemented per column to reduce leakage, then power consumption is reduced, but cell size increases

Engineering Contradiction:

Improveleakage reductionVSAvoidcell size

Core Design Contradiction:

Loss of energyVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared source line serves multiple functions: it acts as the source line for two different columns, provides a virtual ground reference, and can be selectively activated for read operations in either column. This multi-functionality allows the same physical structure to replace what would traditionally require separate dedicated source lines for each column.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Area of stationary object

If shared source lines are used between adjacent columns, then area is reduced and leakage is reduced, but additional diffusion extensions are required

Engineering Contradiction:

Improvearea reductionVSAvoiddiffusion extensions

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent segments the diffusion structure by adding diffusion extensions to the source and drain terminals in specific configurations. These extensions are strategically placed to ensure proper electrical connections when source lines are shared between columns, allowing the diffusion regions to be properly formed and connected without requiring complete redesign of the entire cell structure.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS7609550B2Compact virtual ground diffusion programmable ROM array architecture, system and method

Publication Date: 2009.10.27 SYNOPSYS INC

AI summary

A compact, shared source line and bit line architecture for a diffusion programmable ROM. In one embodiment, a ROM circuit or instance includes a plurality of storage cells organized as an array of rows columns. A shared source line is associated with a first pair of adjacent columns, the shared source line being maintained at a predetermined level, wherein source terminals of storage cells in the adjacent columns are electrically coupled to the shared source line. A shared bit line is associated with a second pair of adjacent columns, the shared bit line being maintained at the predetermined level, wherein drain terminals of storage cells in the adjacent columns are electrically coupled to the shared bit line.