Virtual Ground Memory Programming via Variable Drain Biases
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Solution Overview
Problem
Charge trapping memory devices face issues with non-uniform eraseability and retention loss due to buried drain contact-induced operation, leading to a reduced reliability window and poor endurance, especially as technology scales down.
Innovation Solution
The implementation of a multiple virtual ground (MXVAND) method that applies varying program biases and verify voltage levels to different groups of memory cells, with those adjacent to contacts receiving higher voltages to minimize bit line loading and widen the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single program voltage is applied to all memory cells, then the programming process is simple, but non-uniform eraseability and retention loss occur due to buried drain contact-induced operation
Solution Approach 1:
The patent applies different program voltages to different groups of memory cells based on their location relative to buried drain contacts. Memory cells adjacent to contacts receive higher program voltages than those farther away, creating localized quality variations that compensate for the non-uniform eraseability induced by buried drain contacts.
Solution Approach 2:
The patent divides the array of memory cells into multiple groups based on their distance from buried drain contacts. This segmentation allows independent voltage control for each group, enabling tailored programming conditions that address the specific eraseability characteristics of cells in different locations.
2Reliability
If higher program voltages are applied to contact-adjacent memory cells, then retention window is widened, but bit line loading increases
Solution Approach 1:
The patent applies higher program voltages only to memory cells adjacent to buried drain contacts that require additional programming effort, while using lower voltages for cells farther from contacts. This localized approach widens the retention window for problematic cells without unnecessarily increasing bit line loading across the entire array.
Solution Approach 2:
The patent applies excessive program voltage (higher than standard) only to the specific subset of memory cells that need it (those adjacent to contacts), rather than applying uniform voltage to all cells. This partial excessive action achieves adequate programming for all cells while minimizing overall bit line loading.
3Reliability
If varying program biases are applied to different memory cell groups, then reliability is enhanced, but device complexity increases
Solution Approach 1:
The patent segments memory cells into groups based on their spatial relationship to buried drain contacts and assigns different program voltages to each group. This segmentation strategy enhances programming reliability by accounting for location-dependent eraseability variations while maintaining manageable control complexity through systematic grouping.
Solution Approach 2:
The patent changes the program voltage parameter based on memory cell location relative to buried drain contacts. By systematically varying this electrical parameter according to spatial position, the patent improves programming reliability without requiring complex control mechanisms, as the voltage assignment follows a predictable pattern based on cell group membership.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eases buried drain contact-induced operation, enhances reliability, and increases the retention window by ensuring consistent programming and verification across memory cells, thereby improving the endurance of flash memory devices.
Implementation Method 1
Instead of direct tunneling, band-to-band tunneling induced hot hole injection BTBTHH can be used to erase the cell
Implementation Method 2
the hot hole injection causes oxide damage, leading to charge loss in the high threshold cell and charge gain in the low threshold cell
Implementation Method 3
A frequently used technique to program charge trapping memory cells in a charge trapping memory array is the hot electron injection method
Data Source
AI summary
Methods for programming and program verification of a flash memory are described that ease the buried drain contact induced operation and increase the retention window. In a first aspect of the invention, a program operation method provides varying program biases which are applied to different groups of memory cells. The program biases can be supplied as drain bias voltages or gate bias voltages. The program biases vary depending on which group of memory cells is programmed. In one embodiment, a first drain voltage VD1 is applied to the first group of memory cells M0 and Mn. A second drain voltage VD2 is applied to the second group of memory cells M1 and Mn-1, where VD2=VD1+ΔVD. In a second aspect of the invention, a plurality of program verification voltage levels are selected to verify that the memory cells pass the program voltage levels.