Viterbi Decoder ACS Reuse for Lower-Power Traceback

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Solution Overview

Problem

Viterbi decoders are resource-hungry, particularly in power-constrained environments such as mobile applications, where reducing power consumption is essential for extended device life and efficient communication.

Innovation Solution

The implementation of reduced complexity Viterbi decoding systems that reuse add compare select logic to determine path metrics and identify a best state, reducing the complexity of the decoding process while maintaining effective communication through noisy channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a full Viterbi decoder is used to ensure accurate decoding of signals through noisy channels, then decoding reliability is improved, but power consumption increases

Engineering Contradiction:
Improvedecoding reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The Viterbi decoding process is segmented into distinct phases: an initial phase where the add compare select logic determines path metrics and identifies the best state, and a subsequent phase where the same logic is reused to complete the decoding. This segmentation allows the system to reduce overall computational complexity while maintaining decoding accuracy, thereby reducing power consumption without sacrificing reliability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The add compare select logic is designed to perform multiple functions: it first determines path metrics for signal decoding, then identifies the best state, and finally is reused to complete the decoding process. This multi-functionality eliminates the need for separate dedicated logic units, reducing overall device complexity and power consumption while maintaining full decoding capability and reliability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the add compare select logic continuously determines path metrics for all possible states, then decoding accuracy is maintained, but device complexity increases

Engineering Contradiction:
Improvedecoding accuracyVSAvoiddecoder complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The add compare select logic operates dynamically by adapting its function at different stages of the decoding process. Initially, it performs full path metric determination for all states to ensure accuracy, then transitions to reusing the same logic with modified operations to complete the decoding. This dynamic operation reduces the need for static, complex hardware configurations while maintaining decoding accuracy throughout the process.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8718202B2Reduced complexity viterbi decoding
Publication Date: 2014.05.06 TEXAS INSTRUMENTS INC
  • US8718202B2 patent drawing
  • US8718202B2 patent drawing
  • US8718202B2 patent drawing

AI summary

A system includes a Viterbi decoder. The Viterbi decoder includes add compare select logic. The add compare select logic determines path metrics for an encoded signal. The add compare select logic also is shared to determine a best state by which trace-back procedure gets started, resulting in hardware saving.