Viterbi Decoding Instructions for Low-Power Microcontrollers
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Solution Overview
Problem
Low-cost and low-power microcontrollers struggle to meet the high instruction processing requirements for Viterbi decoding, which is computationally intensive, and dedicated hardware decoders are often too expensive or power-intensive for cost-sensitive applications like power line communication.
Innovation Solution
The implementation of specialized Viterbi decoding instructions that can be executed by a processor or coprocessor to accelerate Viterbi decoding, reducing the need for elevated instruction processing rates and minimizing power dissipation, thereby enhancing processing efficiency without increasing hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Viterbi decoding is performed using standard software instructions on low-cost microcontrollers, then power consumption and hardware complexity remain low, but instruction processing rate is insufficient to meet decoding requirements
Solution Approach 1:
The patent introduces specialized Viterbi decoding instructions that change the operational parameters of the processor by providing optimized instruction sequences specifically designed for Viterbi decoding operations, enabling faster execution without increasing hardware complexity
Solution Approach 2:
The patent introduces a coprocessor as an intermediary component that works alongside the main processor to handle Viterbi decoding operations, allowing the main processor to maintain low power consumption while the coprocessor accelerates decoding at approximately six times the speed of standard instructions
2Productivity
If dedicated hardware Viterbi decoders are used, then decoding speed is improved, but hardware complexity and cost increase significantly
Solution Approach 1:
The patent introduces a coprocessor as an intermediary component that works alongside the main processor to handle Viterbi decoding operations, allowing the main processor to maintain low power consumption while the coprocessor accelerates decoding at approximately six times the speed of standard instructions
Solution Approach 2:
The patent segments the processing functions by separating Viterbi decoding operations from general-purpose processing, dedicating specific coprocessor instructions and hardware resources solely to decoding tasks while leaving the main processor for other system functions
3Productivity
If the processor operates at elevated instruction processing rates to perform Viterbi decoding, then decoding performance is improved, but power dissipation increases
Solution Approach 1:
The patent introduces a coprocessor as an intermediary component that works alongside the main processor to handle Viterbi decoding operations, allowing the main processor to maintain low power consumption while the coprocessor accelerates decoding at approximately six times the speed of standard instructions
Data Source
AI summary
Viterbi decoding is performed on a microcontroller by initializing a state-metric array by executing load instructions to load state-metric data from a memory module into a set of registers in the microcontroller. Butterfly processing on the state-metric array is performed by executing Viterbi processing instructions fetched from a program storage module to manipulate the state-metric (SM) data in the set of registers for each Viterbi butterfly in a stage of Viterbi decoding to form a final set of state-metric data and trace bits. After completing each stage, a final set of state-metric data is stored in the memory module by executing store instructions.