VLSI Test Circuit Array for Transistor Parameter Monitoring
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Solution Overview
Problem
Current transistor monitoring in VLSI processing is limited by the use of single discrete transistors, which are insufficient for accurately monitoring transistor parameters, especially as transistors become more sensitive to process variations due to smaller lithographic dimensions.
Innovation Solution
A test circuit is implemented on a semiconductor wafer with an array of transistors, where decoders are used to selectively pass voltage to the gates, drain, source, and body regions, allowing for comprehensive monitoring of transistor parameters through various testing configurations, such as threshold voltage, bulk gate stress, and gate leakage tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If single discrete transistors are used as monitoring vehicles, then the device complexity is low, but the measurement precision of transistor parameters deteriorates
Solution Approach 1:
The test circuit segments the transistor array into multiple independently controllable units using row decoders and column decoders. Each transistor in the array can be individually selected and tested by activating specific row and column decoder combinations, allowing comprehensive parameter monitoring without requiring a single complex test structure. This segmentation enables precise measurement of multiple transistors simultaneously while maintaining manageable circuit complexity.
Solution Approach 2:
The invention transitions from monitoring a single discrete transistor to monitoring an array of transistors arranged in rows and columns. By adding the spatial dimensions of row and column organization, the system can monitor multiple transistors simultaneously, significantly improving measurement precision and statistical significance while distributing the test circuit complexity across multiple simpler decoder units.
2Manufacturing precision
If transistors are made with smaller lithographic dimensions, then the integration density increases, but the reliability of transistor parameters deteriorates due to increased sensitivity to process variation
Solution Approach 1:
The test circuit performs preliminary characterization of transistor parameters before final device operation. By measuring threshold voltage, bulk gate stress response, and gate leakage characteristics early in the process using the array structure, variations introduced by smaller lithographic dimensions can be detected and compensated for before the transistors are deployed in their final application, thereby maintaining reliability despite reduced dimensions.
Solution Approach 2:
The array-based test circuit provides feedback information about transistor parameter variations across multiple devices. This feedback enables process control adjustments and compensation techniques to be applied, counteracting the increased sensitivity to process variation that arises from smaller lithographic dimensions. The statistical data from multiple transistors helps identify and correct systematic variations.
3Measurement precision
If comprehensive transistor parameter monitoring is implemented, then the measurement precision improves, but the device complexity increases due to multiple decoders and testing configurations
Solution Approach 1:
The test circuit implements multi-functionality by using the same array structure and decoder system to perform multiple different measurements including threshold voltage characterization, bulk gate stress testing, and gate leakage measurement. This universal approach allows comprehensive parameter monitoring without requiring separate dedicated test circuits for each measurement type, thereby improving measurement precision while controlling overall device complexity.
Data Source
AI summary
A test circuit for fabrication of transistors for Very Large Scale Integration (“VLSI”) processing and method of use thereof are described. Transistors are formed in an array. A first decoder is coupled to gates of the transistors and configured to selectively pass voltage to the gates. A second decoder is coupled to drain regions of the transistors and configured to selectively pass voltage to the drain regions of the transistors. A third decoder is coupled to source regions of the transistors and configured to selectively pass voltage to the source regions of the transistors. A fourth decoder is coupled to body regions of the transistors and configured to selectively pass voltage to the body regions of the transistors.