VLIW Data Processing Device with Dynamic Clock Speed Control

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Solution Overview

Problem

VLIW processing devices face high power consumption due to the need to issue many instructions in parallel and access a register file for each instruction, which existing technologies have not effectively addressed.

Innovation Solution

The device employs a combination instruction that allows multiple functional units to respond in series, reducing the number of instructions issued and using a selectable clock rate to minimize power consumption, while also implementing bypass coupling and wave pipelining to optimize instruction execution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If multiple instructions are issued in parallel to functional units, then processing speed is improved, but power consumption increases

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The patent combines multiple instructions into a single combination instruction that can be executed by multiple functional units in series within one instruction cycle. This merging approach reduces the total number of instructions that need to be issued and executed, thereby reducing power consumption while maintaining processing throughput.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces dynamic clock rate selection that adjusts the clock rate based on whether combination instructions are being executed. When combination instructions are present, the clock rate is increased to ensure they complete within one instruction cycle. This dynamic adjustment optimizes power consumption by using higher clock rates only when necessary.

Inventive Principle:
Principle #15Dynamics

2Loss of time

If clock rate is increased to execute combination instructions, then execution time is reduced, but power consumption increases

Engineering Contradiction:
Improveexecution timeVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the clock rate based on the instruction type being executed. When combination instructions are detected, the clock rate is temporarily increased to ensure completion within one instruction cycle. For regular instructions, the clock rate returns to a lower, more power-efficient level. This dynamic adjustment minimizes execution time only when necessary while reducing overall power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the clock rate parameter conditionally based on the presence of combination instructions. By modifying this temporal parameter dynamically, the system achieves fast execution for critical combination instructions while maintaining energy efficiency for the overall program execution.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If many instructions are issued to functional units, then processing capability is improved, but device complexity increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidinstruction issuance complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges multiple individual instructions into a single combination instruction that activates multiple functional units simultaneously. This reduces the number of separate instruction issuance operations needed, simplifying the control logic and reducing device complexity while maintaining the ability to utilize multiple functional units for parallel processing.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7861062B2Data processing device with instruction controlled clock speed
Publication Date: 2010.12.28 KONINKLIJKE PHILIPS NV
  • US7861062B2 patent drawing
  • US7861062B2 patent drawing
  • US7861062B2 patent drawing

AI summary

The data processing device has a plurality of functional units and issues instructions in successive instruction cycles. Instructions of a first type are each intended for one functional unit at a time. An instruction of a second type causes a combination of functional units to respond in the same instruction execution cycle, a result from one functional unit being used by another as part of the execution of the same instruction. Preferably, the device supports alternative operation at a number of different instruction cycle rates, dependent on whether an executed program segment contains instructions of the second type. The fastest instruction cycle rate does not allow execution of the instruction of the second type, because operation by different functional units does not fit within the instruction execution cycle. When possible, the device saves power by switching to a slower clock rate, in which case instructions of the second type are executed to save additional power, by reducing the number of instructions that have to be issued.